OV - exec - Loop 200

	Loop Id: 200	Module: exec	Source: PdV.cpp:69-83 [...]	Coverage: 7.87%

0x428080 SUB	X18, X29, #64

0x428084 MOVPRFX	Z31, Z0

0x428088 SDIV	Z31.D, P0/M, Z31.D, Z2.D

0x42808c MOVPRFX	Z9, Z0

0x428090 MLS	Z9.D, P0/M, Z31.D, Z2.D

0x428094 SUBS	X13, X13, X11

0x428098 LDR	Z1, [X18, #510, MUL VL]    [12]

0x42809c SUB	X18, X29, #64

0x4280a0 ADD	Z30.D, Z1.D, Z31.D

0x4280a4 LDR	Z1, [X18, #509, MUL VL]    [43]

0x4280a8 ADD	Z31.D, Z26.D, Z31.D

0x4280ac MOVPRFX	Z14, Z31

0x4280b0 SXTW	Z14.D, P0/M, Z31.D

0x4280b4 MOVPRFX	Z31, Z6

0x4280b8 MUL	Z31.D, P0/M, Z31.D, Z14.D

0x4280bc SUB	X18, X29, #64

0x4280c0 SXTW	Z30.D, P0/M, Z30.D

0x4280c4 MOVPRFX	Z10, Z5

0x4280c8 MUL	Z10.D, P0/M, Z10.D, Z30.D

0x4280cc MOVPRFX	Z12, Z6

0x4280d0 MUL	Z12.D, P0/M, Z12.D, Z30.D

0x4280d4 ADD	Z8.D, Z1.D, Z9.D

0x4280d8 MOVPRFX	Z1, Z7

0x4280dc MUL	Z1.D, P0/M, Z1.D, Z14.D

0x4280e0 ADD	Z9.D, Z29.D, Z9.D

0x4280e4 ADR	Z11.D, [Z10, Z8.D,SXTW]    [28]

0x4280e8 ADR	Z13.D, [Z12, Z8.D,SXTW]    [10]

0x4280ec ADR	Z15.D, [Z31, Z8.D,SXTW]    [15]

0x4280f0 ADR	Z3.D, [Z1, Z8.D,SXTW]    [8]

0x4280f4 ADR	Z10.D, [Z10, Z9.D,SXTW]    [14]

0x4280f8 ADR	Z12.D, [Z12, Z9.D,SXTW]    [47]

0x4280fc ADR	Z31.D, [Z31, Z9.D,SXTW]    [6]

0x428100 ADR	Z1.D, [Z1, Z9.D,SXTW]    [44]

0x428104 LD1D	{Z11.D}, P0/Z, [X23, Z11.D,LSL #3]    [3]

0x428108 LD1D	{Z13.D}, P0/Z, [X25, Z13.D,LSL #3]    [24]

0x42810c LD1D	{Z15.D}, P0/Z, [X25, Z15.D,LSL #3]    [9]

0x428110 FADD	Z13.D, Z13.D, Z15.D

0x428114 MOVPRFX	Z15, Z7

0x428118 MUL	Z15.D, P0/M, Z15.D, Z30.D

0x42811c ADR	Z28.D, [Z15, Z8.D,SXTW]    [5]

0x428120 LD1D	{Z28.D}, P0/Z, [X27, Z28.D,LSL #3]    [32]

0x428124 LD1D	{Z3.D}, P0/Z, [X27, Z3.D,LSL #3]    [40]

0x428128 LD1RD	{Z4.D}, P0/Z, [X6]    [31]

0x42812c LD1D	{Z10.D}, P0/Z, [X23, Z10.D,LSL #3]    [49]

0x428130 LD1D	{Z12.D}, P0/Z, [X25, Z12.D,LSL #3]    [7]

0x428134 LD1D	{Z31.D}, P0/Z, [X25, Z31.D,LSL #3]    [1]

0x428138 FADD	Z28.D, Z13.D, Z28.D

0x42813c ADR	Z13.D, [Z15, Z9.D,SXTW]    [42]

0x428140 FADD	Z12.D, Z12.D, Z31.D

0x428144 MOVPRFX	Z31, Z8

0x428148 SXTW	Z31.D, P0/M, Z8.D

0x42814c FADD	Z3.D, Z28.D, Z3.D

0x428150 LD1D	{Z28.D}, P0/Z, [X27, Z13.D,LSL #3]    [2]

0x428154 LD1D	{Z1.D}, P0/Z, [X27, Z1.D,LSL #3]    [18]

0x428158 FMUL	Z3.D, Z11.D, Z3.D

0x42815c FADD	Z28.D, Z12.D, Z28.D

0x428160 MOVPRFX	Z12, Z17

0x428164 MUL	Z12.D, P0/M, Z12.D, Z30.D

0x428168 ADR	Z13.D, [Z12, Z8.D,SXTW]    [35]

0x42816c ADR	Z12.D, [Z12, Z9.D,SXTW]    [21]

0x428170 FMUL	Z3.D, Z3.D, Z27.D

0x428174 FADD	Z1.D, Z28.D, Z1.D

0x428178 MOVPRFX	Z28, Z31

0x42817c MLA	Z28.D, P0/M, Z16.D, Z30.D

0x428180 LD1D	{Z28.D}, P0/Z, [X19, Z28.D,LSL #3]    [4]

0x428184 LD1D	{Z11.D}, P0/Z, [X20, Z13.D,LSL #3]    [20]

0x428188 LD1D	{Z12.D}, P0/Z, [X20, Z12.D,LSL #3]    [17]

0x42818c FMUL	Z1.D, Z10.D, Z1.D

0x428190 FMUL	Z3.D, Z4.D, Z3.D

0x428194 FADD	Z11.D, Z11.D, Z12.D

0x428198 MOVPRFX	Z12, Z18

0x42819c MUL	Z12.D, P0/M, Z12.D, Z30.D

0x4281a0 ADR	Z13.D, [Z12, Z8.D,SXTW]    [41]

0x4281a4 ADR	Z12.D, [Z12, Z9.D,SXTW]    [29]

0x4281a8 FMUL	Z1.D, Z1.D, Z27.D

0x4281ac LD1D	{Z13.D}, P0/Z, [X24, Z13.D,LSL #3]    [36]

0x4281b0 LD1D	{Z10.D}, P0/Z, [X24, Z12.D,LSL #3]    [19]

0x4281b4 MOVPRFX	Z12, Z17

0x4281b8 MUL	Z12.D, P0/M, Z12.D, Z14.D

0x4281bc FMUL	Z1.D, Z4.D, Z1.D

0x4281c0 FADD	Z11.D, Z11.D, Z13.D

0x4281c4 ADR	Z13.D, [Z12, Z8.D,SXTW]    [46]

0x4281c8 ADR	Z12.D, [Z12, Z9.D,SXTW]    [34]

0x4281cc FSUB	Z1.D, Z1.D, Z3.D

0x4281d0 MOVPRFX	Z3, Z31

0x4281d4 MLA	Z3.D, P0/M, Z19.D, Z30.D

0x4281d8 FADD	Z10.D, Z11.D, Z10.D

0x4281dc MOVPRFX	Z11, Z31

0x4281e0 MLA	Z11.D, P0/M, Z16.D, Z14.D

0x4281e4 LD1D	{Z11.D}, P0/Z, [X19, Z11.D,LSL #3]    [33]

0x4281e8 LD1D	{Z13.D}, P0/Z, [X20, Z13.D,LSL #3]    [30]

0x4281ec LD1D	{Z12.D}, P0/Z, [X20, Z12.D,LSL #3]    [25]

0x4281f0 FMUL	Z28.D, Z28.D, Z10.D

0x4281f4 FADD	Z10.D, Z13.D, Z12.D

0x4281f8 MOVPRFX	Z12, Z18

0x4281fc MUL	Z12.D, P0/M, Z12.D, Z14.D

0x428200 ADR	Z8.D, [Z12, Z8.D,SXTW]    [37]

0x428204 ADR	Z9.D, [Z12, Z9.D,SXTW]    [22]

0x428208 FMUL	Z28.D, Z28.D, Z27.D

0x42820c LD1D	{Z8.D}, P0/Z, [X24, Z8.D,LSL #3]    [27]

0x428210 LD1D	{Z9.D}, P0/Z, [X24, Z9.D,LSL #3]    [48]

0x428214 LD1D	{Z3.D}, P0/Z, [X8, Z3.D,LSL #3]    [16]

0x428218 FMUL	Z28.D, Z4.D, Z28.D

0x42821c FADD	Z8.D, Z10.D, Z8.D

0x428220 MOVPRFX	Z10, Z31

0x428224 MLA	Z10.D, P0/M, Z22.D, Z30.D

0x428228 FADD	Z8.D, Z8.D, Z9.D

0x42822c FMUL	Z8.D, Z11.D, Z8.D

0x428230 FMUL	Z8.D, Z8.D, Z27.D

0x428234 FMUL	Z4.D, Z4.D, Z8.D

0x428238 MOVPRFX	Z8, Z31

0x42823c MLA	Z8.D, P0/M, Z21.D, Z30.D

0x428240 FADD	Z1.D, Z1.D, Z4.D

0x428244 MOVPRFX	Z4, Z31

0x428248 MLA	Z4.D, P0/M, Z20.D, Z30.D

0x42824c LD1D	{Z4.D}, P0/Z, [X9, Z4.D,LSL #3]    [13]

0x428250 LD1D	{Z9.D}, P0/Z, [X26, Z8.D,LSL #3]    [23]

0x428254 LD1D	{Z10.D}, P0/Z, [X14, Z10.D,LSL #3]    [26]

0x428258 FSUB	Z1.D, Z1.D, Z28.D

0x42825c FDUP	Z28.D, #112

0x428260 FDIV	Z4.D, P0/M, Z4.D, Z9.D

0x428264 FDIVR	Z9.D, P0/M, Z9.D, Z10.D

0x428268 FDIV	Z28.D, P0/M, Z28.D, Z3.D

0x42826c FADD	Z4.D, Z4.D, Z9.D

0x428270 FMUL	Z4.D, Z4.D, Z1.D

0x428274 FADD	Z1.D, Z3.D, Z1.D

0x428278 FDIVR	Z1.D, P0/M, Z1.D, Z3.D

0x42827c FMUL	Z4.D, Z28.D, Z4.D

0x428280 MOVPRFX	Z28, Z31

0x428284 MLA	Z28.D, P0/M, Z23.D, Z30.D

0x428288 LD1D	{Z28.D}, P0/Z, [X16, Z28.D,LSL #3]    [38]

0x42828c FSUB	Z4.D, Z28.D, Z4.D

0x428290 MOVPRFX	Z28, Z31

0x428294 MLA	Z28.D, P0/M, Z24.D, Z30.D

0x428298 ST1D	{Z4.D}, P0, [X15, Z28.D,LSL #3]    [39]

0x42829c LD1D	{Z3.D}, P0/Z, [X26, Z8.D,LSL #3]    [23]

0x4282a0 LDR	Z4, [X18, #511, MUL VL]    [11]

0x4282a4 ADD	Z0.D, Z0.D, Z4.D

0x4282a8 FMUL	Z1.D, Z3.D, Z1.D

0x4282ac MOVPRFX	Z3, Z31

0x4282b0 MLA	Z3.D, P0/M, Z25.D, Z30.D

0x4282b4 ST1D	{Z1.D}, P0, [X17, Z3.D,LSL #3]    [45]

0x4282b8 B.NE	428080

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp: 69 - 83

--------------------------------------------------------------------------------

69: #pragma omp parallel for simd collapse(2)

70:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

71:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.16
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.97
Bottlenecks	P6, P7,
Function	.omp_outlined..2#0x427e20
Source	PdV.cpp:69-83,context.h:69-69
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	53.00
CQA cycles if no scalar integer	53.00
CQA cycles if FP arith vectorized	53.00
CQA cycles if fully vectorized	45.77
Front-end cycles	17.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	53.00
P6 cycles	53.00
P7 cycles	16.50
P8 cycles	16.50
P9 cycles	16.00
P10 cycles	16.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	5.00 - 2.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	143.00
Nb uops	143.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.79
Nb FLOP add-sub	72.00
Nb FLOP mul	60.00
Nb FLOP fma	0.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.87
Bytes prefetched	0.00
Bytes loaded	936.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	69.06
Vectorization ratio load	60.42
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	63.46
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	11.54
Vector-efficiency ratio all	88.51
Vector-efficiency ratio load	70.31
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	72.60
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	96.27

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.16
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.97
Bottlenecks	P6, P7,
Function	.omp_outlined..2#0x427e20
Source	PdV.cpp:69-83,context.h:69-69
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	53.00
CQA cycles if no scalar integer	53.00
CQA cycles if FP arith vectorized	53.00
CQA cycles if fully vectorized	45.77
Front-end cycles	17.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	53.00
P6 cycles	53.00
P7 cycles	16.50
P8 cycles	16.50
P9 cycles	16.00
P10 cycles	16.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	5.00 - 2.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	143.00
Nb uops	143.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.79
Nb FLOP add-sub	72.00
Nb FLOP mul	60.00
Nb FLOP fma	0.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.87
Bytes prefetched	0.00
Bytes loaded	936.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	69.06
Vectorization ratio load	60.42
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	63.46
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	11.54
Vector-efficiency ratio all	88.51
Vector-efficiency ratio load	70.31
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	72.60
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	96.27

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..2#0x427e20
Source file and lines	PdV.cpp:69-83
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:69-83
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 88% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 53.00 to 45.77 cycles (1.16x speedup).

Details

69% of VPU instructions are used in vector version (process two or more data elements in vector registers):

60% of VPU loads are used in vector version.
63% of VPU addition or subtraction instructions are used in vector version.
11% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

72: addition or subtraction
60: multiply
16: divide

The binary loop is loading 936 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	143
loop length	572
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	1.00	1.00	53.00	53.00	1.00	1.00	16.00	16.00	0.00	0.00	0.00
cycles	0.50	0.50	1.00	1.00	1.00	1.00	53.00	53.00	16.50	16.50	16.00	16.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	5.00-2.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	17.88
Data deps.	2.00
Overall L1	53.00

Vectorization ratios

INT

all	58%
load	60%
store	100%
mul	100%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	0%

INT+FP

all	69%
load	60%
store	100%
mul	100%
add-sub	63%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 53.00 cycles. At this rate:

18% of peak load performance is reached (17.66 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.21 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 428080

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
SUB X18, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVPRFX Z31, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z31.D, P0/M, Z31.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z9, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z9.D, P0/M, Z31.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SUBS X13, X13, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
LDR Z1, [X18, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X18, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD Z30.D, Z1.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z1, [X18, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD Z31.D, Z26.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z14, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z14.D, P0/M, Z31.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z31, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z31.D, P0/M, Z31.D, Z14.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SUB X18, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SXTW Z30.D, P0/M, Z30.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z10, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z10.D, P0/M, Z10.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MOVPRFX Z12, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z12.D, P0/M, Z12.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z8.D, Z1.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z1, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z1.D, P0/M, Z1.D, Z14.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z9.D, Z29.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z11.D, [Z10, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z13.D, [Z12, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z15.D, [Z31, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z3.D, [Z1, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z10.D, [Z10, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z12.D, [Z12, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z31.D, [Z31, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z1.D, [Z1, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z11.D}, P0/Z, [X23, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z13.D}, P0/Z, [X25, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z15.D}, P0/Z, [X25, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z13.D, Z13.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z15, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z15.D, P0/M, Z15.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z28.D, [Z15, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z28.D}, P0/Z, [X27, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P0/Z, [X27, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z4.D}, P0/Z, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P0/Z, [X23, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z12.D}, P0/Z, [X25, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X25, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z28.D, Z13.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z13.D, [Z15, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z12.D, Z12.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z31, Z8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z31.D, P0/M, Z8.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
FADD Z3.D, Z28.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z28.D}, P0/Z, [X27, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P0/Z, [X27, Z1.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z3.D, Z11.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z28.D, Z12.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z12, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z12.D, P0/M, Z12.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z13.D, [Z12, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z12.D, [Z12, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z3.D, Z3.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z1.D, Z28.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z28, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z28.D, P0/M, Z16.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z28.D}, P0/Z, [X19, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z11.D}, P0/Z, [X20, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z12.D}, P0/Z, [X20, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z1.D, Z10.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z3.D, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z11.D, Z11.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z12, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z12.D, P0/M, Z12.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z13.D, [Z12, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z12.D, [Z12, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z1.D, Z1.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z13.D}, P0/Z, [X24, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P0/Z, [X24, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z12, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z12.D, P0/M, Z12.D, Z14.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMUL Z1.D, Z4.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z11.D, Z11.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z13.D, [Z12, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z12.D, [Z12, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z1.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z3, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z3.D, P0/M, Z19.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FADD Z10.D, Z11.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z11, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z11.D, P0/M, Z16.D, Z14.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z11.D}, P0/Z, [X19, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z13.D}, P0/Z, [X20, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z12.D}, P0/Z, [X20, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z28.D, Z28.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z10.D, Z13.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z12, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z12.D, P0/M, Z12.D, Z14.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z8.D, [Z12, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z9.D, [Z12, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z28.D, Z28.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z8.D}, P0/Z, [X24, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z9.D}, P0/Z, [X24, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P0/Z, [X8, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z28.D, Z4.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z8.D, Z10.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z10, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z10.D, P0/M, Z22.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FADD Z8.D, Z8.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z8.D, Z11.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z8.D, Z8.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z4.D, Z4.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z8, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z8.D, P0/M, Z21.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FADD Z1.D, Z1.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z4, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z4.D, P0/M, Z20.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z4.D}, P0/Z, [X9, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z9.D}, P0/Z, [X26, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P0/Z, [X14, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z1.D, Z1.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDUP Z28.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z4.D, P0/M, Z4.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z9.D, P0/M, Z9.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIV Z28.D, P0/M, Z28.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z4.D, Z4.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z4.D, Z4.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z1.D, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIVR Z1.D, P0/M, Z1.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z4.D, Z28.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z28, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z28.D, P0/M, Z23.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z28.D}, P0/Z, [X16, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z4.D, Z28.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z28, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z28.D, P0/M, Z24.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z4.D}, P0, [X15, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z3.D}, P0/Z, [X26, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z4, [X18, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD Z0.D, Z0.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z1.D, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z3, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z3.D, P0/M, Z25.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z1.D}, P0, [X17, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 428080 <.omp_outlined..2+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..2#0x427e20
Source file and lines	PdV.cpp:69-83
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:69-83
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

69% of VPU instructions are used in vector version (process two or more data elements in vector registers):

60% of VPU loads are used in vector version.
63% of VPU addition or subtraction instructions are used in vector version.
11% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

72: addition or subtraction
60: multiply
16: divide

The binary loop is loading 936 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	143
loop length	572
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.00	1.00	1.00	1.00	53.00	53.00	1.00	1.00	16.00	16.00	0.00	0.00	0.00
cycles	0.50	0.50	1.00	1.00	1.00	1.00	53.00	53.00	16.50	16.50	16.00	16.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	5.00-2.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	17.88
Data deps.	2.00
Overall L1	53.00

Vectorization ratios

INT

all	58%
load	60%
store	100%
mul	100%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	0%

INT+FP

all	69%
load	60%
store	100%
mul	100%
add-sub	63%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 53.00 cycles. At this rate:

18% of peak load performance is reached (17.66 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.21 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 428080

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
SUB X18, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVPRFX Z31, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z31.D, P0/M, Z31.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z9, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z9.D, P0/M, Z31.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SUBS X13, X13, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
LDR Z1, [X18, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X18, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD Z30.D, Z1.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z1, [X18, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD Z31.D, Z26.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z14, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z14.D, P0/M, Z31.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z31, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z31.D, P0/M, Z31.D, Z14.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SUB X18, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SXTW Z30.D, P0/M, Z30.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z10, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z10.D, P0/M, Z10.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MOVPRFX Z12, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z12.D, P0/M, Z12.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z8.D, Z1.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z1, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z1.D, P0/M, Z1.D, Z14.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z9.D, Z29.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z11.D, [Z10, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z13.D, [Z12, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z15.D, [Z31, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z3.D, [Z1, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z10.D, [Z10, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z12.D, [Z12, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z31.D, [Z31, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z1.D, [Z1, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z11.D}, P0/Z, [X23, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z13.D}, P0/Z, [X25, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z15.D}, P0/Z, [X25, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z13.D, Z13.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z15, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z15.D, P0/M, Z15.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z28.D, [Z15, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z28.D}, P0/Z, [X27, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P0/Z, [X27, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z4.D}, P0/Z, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P0/Z, [X23, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z12.D}, P0/Z, [X25, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X25, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z28.D, Z13.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z13.D, [Z15, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z12.D, Z12.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z31, Z8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z31.D, P0/M, Z8.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
FADD Z3.D, Z28.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z28.D}, P0/Z, [X27, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P0/Z, [X27, Z1.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z3.D, Z11.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z28.D, Z12.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z12, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z12.D, P0/M, Z12.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z13.D, [Z12, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z12.D, [Z12, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z3.D, Z3.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z1.D, Z28.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z28, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z28.D, P0/M, Z16.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z28.D}, P0/Z, [X19, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z11.D}, P0/Z, [X20, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z12.D}, P0/Z, [X20, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z1.D, Z10.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z3.D, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z11.D, Z11.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z12, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z12.D, P0/M, Z12.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z13.D, [Z12, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z12.D, [Z12, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z1.D, Z1.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z13.D}, P0/Z, [X24, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P0/Z, [X24, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z12, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z12.D, P0/M, Z12.D, Z14.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMUL Z1.D, Z4.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z11.D, Z11.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z13.D, [Z12, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z12.D, [Z12, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z1.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z3, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z3.D, P0/M, Z19.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FADD Z10.D, Z11.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z11, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z11.D, P0/M, Z16.D, Z14.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z11.D}, P0/Z, [X19, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z13.D}, P0/Z, [X20, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z12.D}, P0/Z, [X20, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z28.D, Z28.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z10.D, Z13.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z12, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z12.D, P0/M, Z12.D, Z14.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z8.D, [Z12, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z9.D, [Z12, Z9.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z28.D, Z28.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z8.D}, P0/Z, [X24, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z9.D}, P0/Z, [X24, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P0/Z, [X8, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z28.D, Z4.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z8.D, Z10.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z10, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z10.D, P0/M, Z22.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FADD Z8.D, Z8.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z8.D, Z11.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z8.D, Z8.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z4.D, Z4.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z8, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z8.D, P0/M, Z21.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FADD Z1.D, Z1.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z4, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z4.D, P0/M, Z20.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z4.D}, P0/Z, [X9, Z4.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z9.D}, P0/Z, [X26, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P0/Z, [X14, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z1.D, Z1.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDUP Z28.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z4.D, P0/M, Z4.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z9.D, P0/M, Z9.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIV Z28.D, P0/M, Z28.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z4.D, Z4.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z4.D, Z4.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z1.D, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIVR Z1.D, P0/M, Z1.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z4.D, Z28.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z28, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z28.D, P0/M, Z23.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z28.D}, P0/Z, [X16, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z4.D, Z28.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z28, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z28.D, P0/M, Z24.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z4.D}, P0, [X15, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z3.D}, P0/Z, [X26, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LDR Z4, [X18, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD Z0.D, Z0.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z1.D, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z3, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z3.D, P0/M, Z25.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z1.D}, P0, [X17, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 428080 <.omp_outlined..2+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code