OV - exec - Loop 188

	Loop Id: 188	Module: exec	Source: accelerate.cpp:40-53 [...]	Coverage: 7.28%

0x419cc0 SUB	X14, X29, #64

0x419cc4 MOVPRFX	Z28, Z0

0x419cc8 SDIV	Z28.D, P0/M, Z28.D, Z2.D

0x419ccc MOVPRFX	Z27, Z0

0x419cd0 MLS	Z27.D, P0/M, Z28.D, Z2.D

0x419cd4 SUBS	X12, X12, X10

0x419cd8 LDR	Z1, [X14, #510, MUL VL]    [11]

0x419cdc SUB	X14, X29, #64

0x419ce0 ADD	Z29.D, Z1.D, Z28.D

0x419ce4 LDR	Z1, [X14, #509, MUL VL]    [42]

0x419ce8 SUB	X14, X29, #64

0x419cec ADD	Z28.D, Z6.D, Z28.D

0x419cf0 SXTW	Z28.D, P0/M, Z28.D

0x419cf4 MOVPRFX	Z31, Z7

0x419cf8 MUL	Z31.D, P0/M, Z31.D, Z28.D

0x419cfc MOVPRFX	Z9, Z16

0x419d00 MUL	Z9.D, P0/M, Z9.D, Z28.D

0x419d04 SXTW	Z29.D, P0/M, Z29.D

0x419d08 MOVPRFX	Z11, Z7

0x419d0c MUL	Z11.D, P0/M, Z11.D, Z29.D

0x419d10 MOVPRFX	Z13, Z16

0x419d14 MUL	Z13.D, P0/M, Z13.D, Z29.D

0x419d18 ADD	Z26.D, Z1.D, Z27.D

0x419d1c LDR	Z1, [X14, #508, MUL VL]    [34]

0x419d20 LD1RD	{Z30.D}, P0/Z, [X13]    [37]

0x419d24 SUB	X14, X29, #64

0x419d28 ADD	Z27.D, Z1.D, Z27.D

0x419d2c ADR	Z8.D, [Z31, Z27.D,SXTW]    [26]

0x419d30 ADR	Z10.D, [Z9, Z27.D,SXTW]    [24]

0x419d34 ADR	Z12.D, [Z11, Z27.D,SXTW]    [20]

0x419d38 ADR	Z14.D, [Z13, Z27.D,SXTW]    [46]

0x419d3c ADR	Z11.D, [Z11, Z26.D,SXTW]    [38]

0x419d40 ADR	Z31.D, [Z31, Z26.D,SXTW]    [44]

0x419d44 ADR	Z9.D, [Z9, Z26.D,SXTW]    [43]

0x419d48 LD1D	{Z8.D}, P0/Z, [X25, Z8.D,LSL #3]    [36]

0x419d4c LD1D	{Z10.D}, P0/Z, [X27, Z10.D,LSL #3]    [4]

0x419d50 LD1D	{Z12.D}, P0/Z, [X25, Z12.D,LSL #3]    [47]

0x419d54 LD1D	{Z14.D}, P0/Z, [X27, Z14.D,LSL #3]    [19]

0x419d58 LD1D	{Z11.D}, P0/Z, [X25, Z11.D,LSL #3]    [23]

0x419d5c FMUL	Z12.D, Z12.D, Z14.D

0x419d60 MOVPRFX	Z14, Z26

0x419d64 SXTW	Z14.D, P0/M, Z26.D

0x419d68 MOVPRFX	Z24, Z14

0x419d6c MLA	Z24.D, P0/M, Z18.D, Z28.D

0x419d70 FMAD	Z8.D, P0/M, Z10.D, Z12.D

0x419d74 ADR	Z10.D, [Z13, Z26.D,SXTW]    [21]

0x419d78 LD1D	{Z10.D}, P0/Z, [X27, Z10.D,LSL #3]    [10]

0x419d7c LD1D	{Z31.D}, P0/Z, [X25, Z31.D,LSL #3]    [13]

0x419d80 LD1D	{Z9.D}, P0/Z, [X27, Z9.D,LSL #3]    [32]

0x419d84 FMLA	Z8.D, P0/M, Z11.D, Z10.D

0x419d88 MOVPRFX	Z11, Z19

0x419d8c MUL	Z11.D, P0/M, Z11.D, Z29.D

0x419d90 ADR	Z12.D, [Z11, Z26.D,SXTW]    [16]

0x419d94 ADR	Z11.D, [Z11, Z27.D,SXTW]    [35]

0x419d98 MOVPRFX	Z10, Z14

0x419d9c MLA	Z10.D, P0/M, Z17.D, Z29.D

0x419da0 LD1D	{Z10.D}, P0/Z, [X22, Z10.D,LSL #3]    [15]

0x419da4 FMAD	Z31.D, P0/M, Z9.D, Z8.D

0x419da8 MOVPRFX	Z8, Z14

0x419dac MLA	Z8.D, P0/M, Z18.D, Z29.D

0x419db0 LD1D	{Z9.D}, P0/Z, [X21, Z8.D,LSL #3]    [25]

0x419db4 LD1D	{Z13.D}, P0/Z, [X19, Z12.D,LSL #3]    [12]

0x419db8 LD1D	{Z15.D}, P0/Z, [X19, Z11.D,LSL #3]    [40]

0x419dbc LD1D	{Z1.D}, P0/Z, [X21, Z24.D,LSL #3]    [7]

0x419dc0 FSUB	Z13.D, Z13.D, Z15.D

0x419dc4 MOVPRFX	Z15, Z19

0x419dc8 MUL	Z15.D, P0/M, Z15.D, Z28.D

0x419dcc ADR	Z3.D, [Z15, Z26.D,SXTW]    [18]

0x419dd0 ADR	Z15.D, [Z15, Z27.D,SXTW]    [41]

0x419dd4 MUL	Z28.D, P0/M, Z28.D, Z25.D

0x419dd8 LD1D	{Z4.D}, P0/Z, [X19, Z3.D,LSL #3]    [33]

0x419ddc LD1D	{Z5.D}, P0/Z, [X19, Z15.D,LSL #3]    [31]

0x419de0 FSUB	Z4.D, Z4.D, Z5.D

0x419de4 MOVPRFX	Z5, Z30

0x419de8 FNEG	Z5.D, P0/M, Z30.D

0x419dec MOVPRFX	Z30, Z22

0x419df0 MUL	Z30.D, P0/M, Z30.D, Z29.D

0x419df4 FMUL	Z1.D, Z1.D, Z4.D

0x419df8 FDUP	Z4.D, #80

0x419dfc FMUL	Z4.D, Z31.D, Z4.D

0x419e00 ADR	Z31.D, [Z30, Z26.D,SXTW]    [29]

0x419e04 ADR	Z30.D, [Z30, Z27.D,SXTW]    [9]

0x419e08 FMLA	Z1.D, P0/M, Z9.D, Z13.D

0x419e0c FDIVR	Z4.D, P0/M, Z4.D, Z5.D

0x419e10 MOVPRFX	Z5, Z14

0x419e14 MLA	Z5.D, P0/M, Z20.D, Z29.D

0x419e18 FMAD	Z1.D, P0/M, Z4.D, Z10.D

0x419e1c ST1D	{Z1.D}, P0, [X20, Z5.D,LSL #3]    [28]

0x419e20 MOVPRFX	Z1, Z14

0x419e24 MLA	Z1.D, P0/M, Z21.D, Z29.D

0x419e28 LD1D	{Z1.D}, P0/Z, [X8, Z1.D,LSL #3]    [39]

0x419e2c LD1D	{Z9.D}, P0/Z, [X24, Z31.D,LSL #3]    [5]

0x419e30 LD1D	{Z10.D}, P0/Z, [X19, Z12.D,LSL #3]    [12]

0x419e34 LD1D	{Z3.D}, P0/Z, [X19, Z3.D,LSL #3]    [33]

0x419e38 FSUB	Z3.D, Z10.D, Z3.D

0x419e3c LD1D	{Z10.D}, P0/Z, [X24, Z30.D,LSL #3]    [2]

0x419e40 LD1D	{Z11.D}, P0/Z, [X19, Z11.D,LSL #3]    [40]

0x419e44 LD1D	{Z12.D}, P0/Z, [X19, Z15.D,LSL #3]    [31]

0x419e48 FSUB	Z11.D, Z11.D, Z12.D

0x419e4c FMUL	Z10.D, Z10.D, Z11.D

0x419e50 FMAD	Z3.D, P0/M, Z9.D, Z10.D

0x419e54 FMLA	Z1.D, P0/M, Z4.D, Z3.D

0x419e58 MOVPRFX	Z3, Z14

0x419e5c MLA	Z3.D, P0/M, Z23.D, Z29.D

0x419e60 MUL	Z29.D, P0/M, Z29.D, Z25.D

0x419e64 ST1D	{Z1.D}, P0, [X28, Z3.D,LSL #3]    [3]

0x419e68 ADR	Z9.D, [Z29, Z26.D,SXTW]    [6]

0x419e6c ADR	Z29.D, [Z29, Z27.D,SXTW]    [30]

0x419e70 ADR	Z26.D, [Z28, Z26.D,SXTW]    [1]

0x419e74 ADR	Z27.D, [Z28, Z27.D,SXTW]    [27]

0x419e78 LD1D	{Z1.D}, P0/Z, [X20, Z5.D,LSL #3]    [28]

0x419e7c LD1D	{Z8.D}, P0/Z, [X21, Z8.D,LSL #3]    [25]

0x419e80 LD1D	{Z10.D}, P0/Z, [X23, Z9.D,LSL #3]    [45]

0x419e84 LD1D	{Z11.D}, P0/Z, [X23, Z29.D,LSL #3]    [17]

0x419e88 LD1D	{Z24.D}, P0/Z, [X21, Z24.D,LSL #3]    [7]

0x419e8c LD1D	{Z12.D}, P0/Z, [X23, Z26.D,LSL #3]    [22]

0x419e90 LD1D	{Z28.D}, P0/Z, [X23, Z27.D,LSL #3]    [8]

0x419e94 FSUB	Z28.D, Z12.D, Z28.D

0x419e98 FMUL	Z24.D, Z24.D, Z28.D

0x419e9c FSUB	Z28.D, Z10.D, Z11.D

0x419ea0 FMLA	Z24.D, P0/M, Z8.D, Z28.D

0x419ea4 FMLA	Z1.D, P0/M, Z4.D, Z24.D

0x419ea8 ST1D	{Z1.D}, P0, [X20, Z5.D,LSL #3]    [28]

0x419eac LD1D	{Z1.D}, P0/Z, [X28, Z3.D,LSL #3]    [3]

0x419eb0 LD1D	{Z5.D}, P0/Z, [X24, Z31.D,LSL #3]    [5]

0x419eb4 LD1D	{Z24.D}, P0/Z, [X23, Z9.D,LSL #3]    [45]

0x419eb8 LD1D	{Z26.D}, P0/Z, [X23, Z26.D,LSL #3]    [22]

0x419ebc LD1D	{Z28.D}, P0/Z, [X24, Z30.D,LSL #3]    [2]

0x419ec0 FSUB	Z24.D, Z24.D, Z26.D

0x419ec4 LD1D	{Z26.D}, P0/Z, [X23, Z29.D,LSL #3]    [17]

0x419ec8 LD1D	{Z27.D}, P0/Z, [X23, Z27.D,LSL #3]    [8]

0x419ecc FSUB	Z26.D, Z26.D, Z27.D

0x419ed0 FMUL	Z26.D, Z28.D, Z26.D

0x419ed4 FMAD	Z5.D, P0/M, Z24.D, Z26.D

0x419ed8 FMLA	Z1.D, P0/M, Z4.D, Z5.D

0x419edc LDR	Z4, [X14, #511, MUL VL]    [14]

0x419ee0 ST1D	{Z1.D}, P0, [X28, Z3.D,LSL #3]    [3]

0x419ee4 ADD	Z0.D, Z0.D, Z4.D

0x419ee8 B.NE	419cc0

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/accelerate.cpp: 40 - 53

--------------------------------------------------------------------------------

40: #pragma omp parallel for simd collapse(2)

41:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

42:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

43:       double stepbymass_s = halfdt / ((density0(i - 1, j - 1) * volume(i - 1, j - 1) + density0(i - 1, j + 0) * volume(i - 1, j + 0) +

44:                                        density0(i, j) * volume(i, j) + density0(i + 0, j - 1) * volume(i + 0, j - 1)) *

45:                                       0.25);

46:       xvel1(i, j) = xvel0(i, j) - stepbymass_s * (xarea(i, j) * (pressure(i, j) - pressure(i - 1, j + 0)) +

47:                                                   xarea(i + 0, j - 1) * (pressure(i + 0, j - 1) - pressure(i - 1, j - 1)));

48:       yvel1(i, j) = yvel0(i, j) - stepbymass_s * (yarea(i, j) * (pressure(i, j) - pressure(i + 0, j - 1)) +

49:                                                   yarea(i - 1, j + 0) * (pressure(i - 1, j + 0) - pressure(i - 1, j - 1)));

50:       xvel1(i, j) = xvel1(i, j) - stepbymass_s * (xarea(i, j) * (viscosity(i, j) - viscosity(i - 1, j + 0)) +

51:                                                   xarea(i + 0, j - 1) * (viscosity(i + 0, j - 1) - viscosity(i - 1, j - 1)));

52:       yvel1(i, j) = yvel1(i, j) - stepbymass_s * (yarea(i, j) * (viscosity(i, j) - viscosity(i + 0, j - 1)) +

53:                                                   yarea(i - 1, j + 0) * (viscosity(i - 1, j + 0) - viscosity(i - 1, j - 1)));

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.96
Bottlenecks	P6, P7,
Function	.omp_outlined.
Source	context.h:69-69,accelerate.cpp:40-53
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	44.00
CQA cycles if no scalar integer	44.00
CQA cycles if FP arith vectorized	44.00
CQA cycles if fully vectorized	36.77
Front-end cycles	17.38
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	44.00
P6 cycles	44.00
P7 cycles	12.50
P8 cycles	12.50
P9 cycles	22.50
P10 cycles	22.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00 - 1.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	139.00
Nb uops	139.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	3.36
Nb FLOP add-sub	32.00
Nb FLOP mul	24.00
Nb FLOP fma	44.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.18
Bytes prefetched	0.00
Bytes loaded	1288.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	71.64
Vectorization ratio load	67.80
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	51.28
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	18.18
Vector-efficiency ratio all	88.08
Vector-efficiency ratio load	75.85
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	63.46
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	95.60

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.20
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.96
Bottlenecks	P6, P7,
Function	.omp_outlined.
Source	context.h:69-69,accelerate.cpp:40-53
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	44.00
CQA cycles if no scalar integer	44.00
CQA cycles if FP arith vectorized	44.00
CQA cycles if fully vectorized	36.77
Front-end cycles	17.38
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	44.00
P6 cycles	44.00
P7 cycles	12.50
P8 cycles	12.50
P9 cycles	22.50
P10 cycles	22.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00 - 1.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	139.00
Nb uops	139.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	3.36
Nb FLOP add-sub	32.00
Nb FLOP mul	24.00
Nb FLOP fma	44.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.18
Bytes prefetched	0.00
Bytes loaded	1288.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	71.64
Vectorization ratio load	67.80
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	51.28
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	18.18
Vector-efficiency ratio all	88.08
Vector-efficiency ratio load	75.85
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	63.46
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	95.60

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.
Source file and lines	accelerate.cpp:40-53
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/accelerate.cpp:40-53

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 88% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 44.00 to 36.77 cycles (1.20x speedup).

Details

71% of VPU instructions are used in vector version (process two or more data elements in vector registers):

67% of VPU loads are used in vector version.
51% of VPU addition or subtraction instructions are used in vector version.
18% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 44 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

76: addition or subtraction (44 inside FMA instructions)
68: multiply (44 inside FMA instructions)
4: divide

The binary loop is loading 1288 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	139
loop length	556
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.25	1.25	1.25	1.25	44.00	44.00	2.00	2.00	22.50	22.50	0.00	0.00	0.00
cycles	0.50	0.50	1.25	1.25	1.25	1.25	44.00	44.00	12.50	12.50	22.50	22.50	0.00	0.00	0.00

Cycles executing div or sqrt instructions	2.00-1.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	17.38
Data deps.	2.00
Overall L1	44.00

Vectorization ratios

INT

all	65%
load	67%
store	100%
mul	100%
add-sub	38%
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	50%

INT+FP

all	71%
load	67%
store	100%
mul	100%
add-sub	51%
fma	100%
div/sqrt	100%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 44.00 cycles. At this rate:

30% of peak load performance is reached (29.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (2.91 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 419cc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
SUB X14, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVPRFX Z28, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z28.D, P0/M, Z28.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z27, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z27.D, P0/M, Z28.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
LDR Z1, [X14, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X14, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD Z29.D, Z1.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z1, [X14, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X14, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD Z28.D, Z6.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z28.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z31, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z31.D, P0/M, Z31.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MOVPRFX Z9, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z9.D, P0/M, Z9.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SXTW Z29.D, P0/M, Z29.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z11, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z11.D, P0/M, Z11.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MOVPRFX Z13, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z13.D, P0/M, Z13.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z26.D, Z1.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z1, [X14, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z30.D}, P0/Z, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X14, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD Z27.D, Z1.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z8.D, [Z31, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z10.D, [Z9, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z12.D, [Z11, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z14.D, [Z13, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z11.D, [Z11, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z31.D, [Z31, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z9.D, [Z9, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z8.D}, P0/Z, [X25, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P0/Z, [X27, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z12.D}, P0/Z, [X25, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z14.D}, P0/Z, [X27, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z11.D}, P0/Z, [X25, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z12.D, Z12.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z14, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z14.D, P0/M, Z26.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z24, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z18.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMAD Z8.D, P0/M, Z10.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADR Z10.D, [Z13, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z10.D}, P0/Z, [X27, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X25, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z9.D}, P0/Z, [X27, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z8.D, P0/M, Z11.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z11, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z11.D, P0/M, Z11.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z12.D, [Z11, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z11.D, [Z11, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z10, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z10.D, P0/M, Z17.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z10.D}, P0/Z, [X22, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z31.D, P0/M, Z9.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z8, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z8.D, P0/M, Z18.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z9.D}, P0/Z, [X21, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z13.D}, P0/Z, [X19, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z15.D}, P0/Z, [X19, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P0/Z, [X21, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z13.D, Z13.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z15, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z15.D, P0/M, Z15.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z3.D, [Z15, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z15.D, [Z15, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z28.D, P0/M, Z28.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z4.D}, P0/Z, [X19, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P0/Z, [X19, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z4.D, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z5, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z5.D, P0/M, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z30, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z30.D, P0/M, Z30.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMUL Z1.D, Z1.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDUP Z4.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z4.D, Z31.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADR Z31.D, [Z30, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z30.D, [Z30, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z1.D, P0/M, Z9.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIVR Z4.D, P0/M, Z4.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z5, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z5.D, P0/M, Z20.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMAD Z1.D, P0/M, Z4.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z1.D}, P0, [X20, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z1, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z1.D, P0/M, Z21.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z1.D}, P0/Z, [X8, Z1.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z9.D}, P0/Z, [X24, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P0/Z, [X19, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P0/Z, [X19, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z3.D, Z10.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z10.D}, P0/Z, [X24, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z11.D}, P0/Z, [X19, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z12.D}, P0/Z, [X19, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z11.D, Z11.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, Z10.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z3.D, P0/M, Z9.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z1.D, P0/M, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z3, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z3.D, P0/M, Z23.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MUL Z29.D, P0/M, Z29.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z1.D}, P0, [X28, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADR Z9.D, [Z29, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z29.D, [Z29, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z26.D, [Z28, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z27.D, [Z28, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z1.D}, P0/Z, [X20, Z5.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z8.D}, P0/Z, [X21, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P0/Z, [X23, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z11.D}, P0/Z, [X23, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P0/Z, [X21, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z12.D}, P0/Z, [X23, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P0/Z, [X23, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z28.D, Z12.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z24.D, Z24.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z28.D, Z10.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z24.D, P0/M, Z8.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z1.D, P0/M, Z4.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z1.D}, P0, [X20, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z1.D}, P0/Z, [X28, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P0/Z, [X24, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P0/Z, [X23, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P0/Z, [X23, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P0/Z, [X24, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z24.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z26.D}, P0/Z, [X23, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z27.D}, P0/Z, [X23, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z26.D, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z26.D, Z28.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z5.D, P0/M, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z1.D, P0/M, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z4, [X14, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z1.D}, P0, [X28, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD Z0.D, Z0.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
B.NE 419cc0 <.omp_outlined.+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.
Source file and lines	accelerate.cpp:40-53
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/accelerate.cpp:40-53

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

71% of VPU instructions are used in vector version (process two or more data elements in vector registers):

67% of VPU loads are used in vector version.
51% of VPU addition or subtraction instructions are used in vector version.
18% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 44 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

76: addition or subtraction (44 inside FMA instructions)
68: multiply (44 inside FMA instructions)
4: divide

The binary loop is loading 1288 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	139
loop length	556
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.25	1.25	1.25	1.25	44.00	44.00	2.00	2.00	22.50	22.50	0.00	0.00	0.00
cycles	0.50	0.50	1.25	1.25	1.25	1.25	44.00	44.00	12.50	12.50	22.50	22.50	0.00	0.00	0.00

Cycles executing div or sqrt instructions	2.00-1.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	17.38
Data deps.	2.00
Overall L1	44.00

Vectorization ratios

INT

all	65%
load	67%
store	100%
mul	100%
add-sub	38%
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	50%

INT+FP

all	71%
load	67%
store	100%
mul	100%
add-sub	51%
fma	100%
div/sqrt	100%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 44.00 cycles. At this rate:

30% of peak load performance is reached (29.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (2.91 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 419cc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
SUB X14, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVPRFX Z28, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z28.D, P0/M, Z28.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z27, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z27.D, P0/M, Z28.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
LDR Z1, [X14, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X14, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD Z29.D, Z1.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z1, [X14, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X14, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD Z28.D, Z6.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z28.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z31, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z31.D, P0/M, Z31.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MOVPRFX Z9, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z9.D, P0/M, Z9.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SXTW Z29.D, P0/M, Z29.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z11, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z11.D, P0/M, Z11.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MOVPRFX Z13, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z13.D, P0/M, Z13.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z26.D, Z1.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LDR Z1, [X14, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z30.D}, P0/Z, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUB X14, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD Z27.D, Z1.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z8.D, [Z31, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z10.D, [Z9, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z12.D, [Z11, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z14.D, [Z13, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z11.D, [Z11, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z31.D, [Z31, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z9.D, [Z9, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z8.D}, P0/Z, [X25, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P0/Z, [X27, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z12.D}, P0/Z, [X25, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z14.D}, P0/Z, [X27, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z11.D}, P0/Z, [X25, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z12.D, Z12.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z14, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z14.D, P0/M, Z26.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z24, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z24.D, P0/M, Z18.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMAD Z8.D, P0/M, Z10.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ADR Z10.D, [Z13, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z10.D}, P0/Z, [X27, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X25, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z9.D}, P0/Z, [X27, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLA Z8.D, P0/M, Z11.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z11, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z11.D, P0/M, Z11.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z12.D, [Z11, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z11.D, [Z11, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z10, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z10.D, P0/M, Z17.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z10.D}, P0/Z, [X22, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z31.D, P0/M, Z9.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z8, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z8.D, P0/M, Z18.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z9.D}, P0/Z, [X21, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z13.D}, P0/Z, [X19, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z15.D}, P0/Z, [X19, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P0/Z, [X21, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z13.D, Z13.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z15, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z15.D, P0/M, Z15.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z3.D, [Z15, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z15.D, [Z15, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z28.D, P0/M, Z28.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z4.D}, P0/Z, [X19, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P0/Z, [X19, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z4.D, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z5, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z5.D, P0/M, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z30, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z30.D, P0/M, Z30.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMUL Z1.D, Z1.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDUP Z4.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z4.D, Z31.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADR Z31.D, [Z30, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z30.D, [Z30, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z1.D, P0/M, Z9.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIVR Z4.D, P0/M, Z4.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z5, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z5.D, P0/M, Z20.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMAD Z1.D, P0/M, Z4.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z1.D}, P0, [X20, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
MOVPRFX Z1, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z1.D, P0/M, Z21.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z1.D}, P0/Z, [X8, Z1.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z9.D}, P0/Z, [X24, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P0/Z, [X19, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P0/Z, [X19, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z3.D, Z10.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z10.D}, P0/Z, [X24, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z11.D}, P0/Z, [X19, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z12.D}, P0/Z, [X19, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z11.D, Z11.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, Z10.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z3.D, P0/M, Z9.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z1.D, P0/M, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z3, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z3.D, P0/M, Z23.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MUL Z29.D, P0/M, Z29.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z1.D}, P0, [X28, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADR Z9.D, [Z29, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z29.D, [Z29, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z26.D, [Z28, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z27.D, [Z28, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z1.D}, P0/Z, [X20, Z5.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z8.D}, P0/Z, [X21, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P0/Z, [X23, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z11.D}, P0/Z, [X23, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P0/Z, [X21, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z12.D}, P0/Z, [X23, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P0/Z, [X23, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z28.D, Z12.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z24.D, Z24.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z28.D, Z10.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z24.D, P0/M, Z8.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z1.D, P0/M, Z4.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z1.D}, P0, [X20, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z1.D}, P0/Z, [X28, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P0/Z, [X24, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P0/Z, [X23, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P0/Z, [X23, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P0/Z, [X24, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z24.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z26.D}, P0/Z, [X23, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z27.D}, P0/Z, [X23, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z26.D, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z26.D, Z28.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z5.D, P0/M, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMLA Z1.D, P0/M, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LDR Z4, [X14, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z1.D}, P0, [X28, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD Z0.D, Z0.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
B.NE 419cc0 <.omp_outlined.+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code