OV - exec - Loop 186

	Loop Id: 186	Module: exec	Source: advec_cell.cpp:45-48 [...]	Coverage: 1.34%

0x41a660 MOVPRFX	Z20, Z0

0x41a664 SDIV	Z20.D, P0/M, Z20.D, Z2.D

0x41a668 ADD	Z21.D, Z3.D, Z20.D

0x41a66c MOVPRFX	Z22, Z0

0x41a670 MLS	Z22.D, P0/M, Z20.D, Z2.D

0x41a674 ADD	Z20.D, Z16.D, Z20.D

0x41a678 SUBS	X12, X12, X10

0x41a67c ADD	Z23.D, Z4.D, Z22.D

0x41a680 MOVPRFX	Z24, Z23

0x41a684 SXTW	Z24.D, P0/M, Z23.D

0x41a688 ADD	Z22.D, Z6.D, Z22.D

0x41a68c ADD	Z0.D, Z0.D, Z1.D

0x41a690 SXTW	Z20.D, P0/M, Z20.D

0x41a694 SXTW	Z21.D, P0/M, Z21.D

0x41a698 MOVPRFX	Z26, Z7

0x41a69c MUL	Z26.D, P0/M, Z26.D, Z21.D

0x41a6a0 MOVPRFX	Z25, Z24

0x41a6a4 MLA	Z25.D, P0/M, Z5.D, Z21.D

0x41a6a8 LD1D	{Z25.D}, P0/Z, [X24, Z25.D,LSL #3]    [3]

0x41a6ac ADR	Z22.D, [Z26, Z22.D,SXTW]    [4]

0x41a6b0 LD1D	{Z27.D}, P0/Z, [X26, Z22.D,LSL #3]    [2]

0x41a6b4 MAD	Z20.D, P0/M, Z17.D, Z24.D

0x41a6b8 ADR	Z23.D, [Z26, Z23.D,SXTW]    [6]

0x41a6bc LD1D	{Z26.D}, P0/Z, [X26, Z23.D,LSL #3]    [8]

0x41a6c0 LD1D	{Z20.D}, P0/Z, [X28, Z20.D,LSL #3]    [5]

0x41a6c4 FSUB	Z26.D, Z27.D, Z26.D

0x41a6c8 FADD	Z20.D, Z26.D, Z20.D

0x41a6cc MOVPRFX	Z26, Z24

0x41a6d0 MLA	Z26.D, P0/M, Z17.D, Z21.D

0x41a6d4 LD1D	{Z26.D}, P0/Z, [X28, Z26.D,LSL #3]    [1]

0x41a6d8 FSUB	Z20.D, Z20.D, Z26.D

0x41a6dc FADD	Z20.D, Z25.D, Z20.D

0x41a6e0 MOVPRFX	Z25, Z24

0x41a6e4 MLA	Z25.D, P0/M, Z18.D, Z21.D

0x41a6e8 MAD	Z21.D, P0/M, Z19.D, Z24.D

0x41a6ec ST1D	{Z20.D}, P0, [X22, Z25.D,LSL #3]    [9]

0x41a6f0 LD1D	{Z22.D}, P0/Z, [X26, Z22.D,LSL #3]    [2]

0x41a6f4 LD1D	{Z23.D}, P0/Z, [X26, Z23.D,LSL #3]    [8]

0x41a6f8 FSUB	Z22.D, Z22.D, Z23.D

0x41a6fc FSUB	Z20.D, Z20.D, Z22.D

0x41a700 ST1D	{Z20.D}, P0, [X21, Z21.D,LSL #3]    [7]

0x41a704 B.NE	41a660

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 45 - 48

--------------------------------------------------------------------------------

45:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

46:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

47:           pre_vol(i, j) = volume(i, j) + (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j));

48:           post_vol(i, j) = pre_vol(i, j) - (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j));

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.05
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.95
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x41a4f0
Source	advec_cell.cpp:45-48,context.h:69-69
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	15.50
CQA cycles if no scalar integer	15.50
CQA cycles if FP arith vectorized	15.50
CQA cycles if fully vectorized	14.75
Front-end cycles	5.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	15.50
P6 cycles	15.50
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	4.50
P10 cycles	4.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.55
Nb FLOP add-sub	24.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.58
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	75.61
Vectorization ratio load	77.78
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	83.33
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	30.00
Vector-efficiency ratio all	94.51
Vector-efficiency ratio load	83.33
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	87.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.05
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.95
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x41a4f0
Source	advec_cell.cpp:45-48,context.h:69-69
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	15.50
CQA cycles if no scalar integer	15.50
CQA cycles if FP arith vectorized	15.50
CQA cycles if fully vectorized	14.75
Front-end cycles	5.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	15.50
P6 cycles	15.50
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	4.50
P10 cycles	4.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.55
Nb FLOP add-sub	24.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.58
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	75.61
Vectorization ratio load	77.78
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	83.33
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	30.00
Vector-efficiency ratio all	94.51
Vector-efficiency ratio load	83.33
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	87.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x41a4f0
Source file and lines	advec_cell.cpp:45-48
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:45-48
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 94% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 15.50 to 14.75 cycles (1.05x speedup).

Details

75% of VPU instructions are used in vector version (process two or more data elements in vector registers):

77% of VPU loads are used in vector version.
83% of VPU addition or subtraction instructions are used in vector version.
30% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

24: addition or subtraction

The binary loop is loading 224 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	15.50	15.50	1.00	1.00	4.50	4.50	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	15.50	15.50	3.00	3.00	4.50	4.50	0.00	0.00	0.00

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	5.25
Data deps.	2.00
Overall L1	15.50

Vectorization ratios

INT

all	71%
load	77%
store	100%
mul	100%
add-sub	75%
fma	100%
other	36%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	75%
load	77%
store	100%
mul	100%
add-sub	83%
fma	100%
div/sqrt	100%
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.50 cycles. At this rate:

15% of peak load performance is reached (14.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.13 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41a660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z20, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z20.D, P0/M, Z20.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z21.D, Z3.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z22, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z22.D, P0/M, Z20.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z20.D, Z16.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z23.D, Z4.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z24, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z24.D, P0/M, Z23.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z22.D, Z6.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z20.D, P0/M, Z20.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z21.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z26, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z26.D, P0/M, Z26.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z5.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z25.D}, P0/Z, [X24, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z22.D, [Z26, Z22.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z27.D}, P0/Z, [X26, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z20.D, P0/M, Z17.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z23.D, [Z26, Z23.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z26.D}, P0/Z, [X26, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X28, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z26.D, Z27.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z20.D, Z26.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z26, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z26.D, P0/M, Z17.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z26.D}, P0/Z, [X28, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z20.D, Z20.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z20.D, Z25.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z18.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MAD Z21.D, P0/M, Z19.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z20.D}, P0, [X22, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z22.D}, P0/Z, [X26, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P0/Z, [X26, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z22.D, Z22.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z20.D, Z20.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z20.D}, P0, [X21, Z21.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41a660 <.omp_outlined.+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x41a4f0
Source file and lines	advec_cell.cpp:45-48
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:45-48
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

75% of VPU instructions are used in vector version (process two or more data elements in vector registers):

77% of VPU loads are used in vector version.
83% of VPU addition or subtraction instructions are used in vector version.
30% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

24: addition or subtraction

The binary loop is loading 224 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	15.50	15.50	1.00	1.00	4.50	4.50	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	15.50	15.50	3.00	3.00	4.50	4.50	0.00	0.00	0.00

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	5.25
Data deps.	2.00
Overall L1	15.50

Vectorization ratios

INT

all	71%
load	77%
store	100%
mul	100%
add-sub	75%
fma	100%
other	36%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	75%
load	77%
store	100%
mul	100%
add-sub	83%
fma	100%
div/sqrt	100%
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.50 cycles. At this rate:

15% of peak load performance is reached (14.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.13 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41a660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z20, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z20.D, P0/M, Z20.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z21.D, Z3.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z22, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z22.D, P0/M, Z20.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z20.D, Z16.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z23.D, Z4.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z24, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z24.D, P0/M, Z23.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
ADD Z22.D, Z6.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z20.D, P0/M, Z20.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SXTW Z21.D, P0/M, Z21.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z26, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z26.D, P0/M, Z26.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z5.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z25.D}, P0/Z, [X24, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z22.D, [Z26, Z22.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z27.D}, P0/Z, [X26, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z20.D, P0/M, Z17.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z23.D, [Z26, Z23.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z26.D}, P0/Z, [X26, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X28, Z20.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z26.D, Z27.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z20.D, Z26.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z26, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z26.D, P0/M, Z17.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z26.D}, P0/Z, [X28, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z20.D, Z20.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z20.D, Z25.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z25.D, P0/M, Z18.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MAD Z21.D, P0/M, Z19.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z20.D}, P0, [X22, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z22.D}, P0/Z, [X26, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P0/Z, [X26, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z22.D, Z22.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z20.D, Z20.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z20.D}, P0, [X21, Z21.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 41a660 <.omp_outlined.+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code