OV - exec - Loop 171

	Loop Id: 171	Module: exec	Source: flux_calc.cpp:36-40 [...]	Coverage: 4.48%

0x422000 LDR	D28, [X19]    [17]

0x422004 MOVPRFX	Z24, Z0

0x422008 SDIV	Z24.D, P0/M, Z24.D, Z2.D

0x42200c ADD	Z25.D, Z3.D, Z24.D

0x422010 MOVPRFX	Z26, Z0

0x422014 MLS	Z26.D, P0/M, Z24.D, Z2.D

0x422018 ADD	Z27.D, Z4.D, Z26.D

0x42201c MOVPRFX	Z29, Z27

0x422020 SXTW	Z29.D, P0/M, Z27.D

0x422024 SUBS	X12, X12, X10

0x422028 ADD	Z24.D, Z21.D, Z24.D

0x42202c ADD	Z26.D, Z23.D, Z26.D

0x422030 ADD	Z0.D, Z0.D, Z1.D

0x422034 SXTW	Z25.D, P0/M, Z25.D

0x422038 MOVPRFX	Z30, Z29

0x42203c MLA	Z30.D, P0/M, Z5.D, Z25.D

0x422040 LD1D	{Z30.D}, P0/Z, [X8, Z30.D,LSL #3]    [5]

0x422044 MOVPRFX	Z31, Z29

0x422048 MLA	Z31.D, P0/M, Z6.D, Z25.D

0x42204c LD1D	{Z31.D}, P0/Z, [X28, Z31.D,LSL #3]    [12]

0x422050 SXTW	Z24.D, P0/M, Z24.D

0x422054 FMUL	D28, D28, D22

0x422058 DUP	Z28.D, Z28.D[0]

0x42205c FMUL	Z28.D, Z28.D, Z30.D

0x422060 MOVPRFX	Z30, Z29

0x422064 MLA	Z30.D, P0/M, Z6.D, Z24.D

0x422068 LD1D	{Z30.D}, P0/Z, [X28, Z30.D,LSL #3]    [10]

0x42206c MAD	Z24.D, P0/M, Z7.D, Z29.D

0x422070 FADD	Z30.D, Z31.D, Z30.D

0x422074 MOVPRFX	Z31, Z29

0x422078 MLA	Z31.D, P0/M, Z7.D, Z25.D

0x42207c LD1D	{Z31.D}, P0/Z, [X23, Z31.D,LSL #3]    [11]

0x422080 LD1D	{Z24.D}, P0/Z, [X23, Z24.D,LSL #3]    [15]

0x422084 FADD	Z30.D, Z30.D, Z31.D

0x422088 FADD	Z24.D, Z30.D, Z24.D

0x42208c MOVPRFX	Z30, Z18

0x422090 MUL	Z30.D, P0/M, Z30.D, Z25.D

0x422094 ADR	Z31.D, [Z30, Z27.D,SXTW]    [14]

0x422098 ADR	Z30.D, [Z30, Z26.D,SXTW]    [6]

0x42209c FMUL	Z24.D, Z28.D, Z24.D

0x4220a0 MOVPRFX	Z28, Z29

0x4220a4 MLA	Z28.D, P0/M, Z16.D, Z25.D

0x4220a8 ST1D	{Z24.D}, P0, [X13, Z28.D,LSL #3]    [13]

0x4220ac MOVPRFX	Z28, Z29

0x4220b0 MLA	Z28.D, P0/M, Z17.D, Z25.D

0x4220b4 LDR	D24, [X19]    [17]

0x4220b8 LD1D	{Z28.D}, P0/Z, [X21, Z28.D,LSL #3]    [7]

0x4220bc LD1D	{Z31.D}, P0/Z, [X22, Z31.D,LSL #3]    [8]

0x4220c0 LD1D	{Z30.D}, P0/Z, [X22, Z30.D,LSL #3]    [3]

0x4220c4 FADD	Z30.D, Z31.D, Z30.D

0x4220c8 MOVPRFX	Z31, Z19

0x4220cc MUL	Z31.D, P0/M, Z31.D, Z25.D

0x4220d0 ADR	Z27.D, [Z31, Z27.D,SXTW]    [2]

0x4220d4 ADR	Z26.D, [Z31, Z26.D,SXTW]    [4]

0x4220d8 MAD	Z25.D, P0/M, Z20.D, Z29.D

0x4220dc FMUL	D24, D24, D22

0x4220e0 LD1D	{Z27.D}, P0/Z, [X24, Z27.D,LSL #3]    [9]

0x4220e4 LD1D	{Z26.D}, P0/Z, [X24, Z26.D,LSL #3]    [16]

0x4220e8 DUP	Z24.D, Z24.D[0]

0x4220ec FADD	Z27.D, Z30.D, Z27.D

0x4220f0 FMUL	Z24.D, Z24.D, Z28.D

0x4220f4 FADD	Z26.D, Z27.D, Z26.D

0x4220f8 FMUL	Z24.D, Z24.D, Z26.D

0x4220fc ST1D	{Z24.D}, P0, [X25, Z25.D,LSL #3]    [1]

0x422100 B.NE	422000

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/flux_calc.cpp: 36 - 40

--------------------------------------------------------------------------------

36: #pragma omp parallel for simd collapse(2)

37:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

39:       vol_flux_x(i, j) = 0.25 * dt * xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1));

40:       vol_flux_y(i, j) = 0.25 * dt * yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0));

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.07
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.89
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x421e30
Source	context.h:69-69,flux_calc.cpp:36-40
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	23.50
CQA cycles if no scalar integer	23.50
CQA cycles if FP arith vectorized	23.50
CQA cycles if fully vectorized	22.00
Front-end cycles	8.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	23.50
P6 cycles	23.50
P7 cycles	5.50
P8 cycles	5.50
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	65.00
Nb uops	65.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.79
Nb FLOP add-sub	24.00
Nb FLOP mul	18.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.02
Bytes prefetched	0.00
Bytes loaded	336.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	70.97
Vectorization ratio load	62.50
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	78.26
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	31.25
Vector-efficiency ratio all	91.53
Vector-efficiency ratio load	71.88
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	83.70
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.07
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.89
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x421e30
Source	context.h:69-69,flux_calc.cpp:36-40
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	23.50
CQA cycles if no scalar integer	23.50
CQA cycles if FP arith vectorized	23.50
CQA cycles if fully vectorized	22.00
Front-end cycles	8.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	23.50
P6 cycles	23.50
P7 cycles	5.50
P8 cycles	5.50
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	65.00
Nb uops	65.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.79
Nb FLOP add-sub	24.00
Nb FLOP mul	18.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.02
Bytes prefetched	0.00
Bytes loaded	336.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	70.97
Vectorization ratio load	62.50
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	78.26
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	31.25
Vector-efficiency ratio all	91.53
Vector-efficiency ratio load	71.88
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	83.70
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x421e30
Source file and lines	flux_calc.cpp:36-40
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/flux_calc.cpp:36-40

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 91% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 23.50 to 22.00 cycles (1.07x speedup).

Details

70% of VPU instructions are used in vector version (process two or more data elements in vector registers):

62% of VPU loads are used in vector version.
78% of VPU addition or subtraction instructions are used in vector version.
31% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 42 FP arithmetical operations:

24: addition or subtraction
18: multiply

The binary loop is loading 336 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	65
loop length	260
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	23.50	23.50	2.00	2.00	6.00	6.00	2.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	23.50	23.50	5.50	5.50	6.00	6.00	2.00	0.00	0.00

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.13
Data deps.	2.00
Overall L1	23.50

Vectorization ratios

INT

all	65%
load	62%
store	100%
mul	100%
add-sub	70%
fma	100%
other	35%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	70%
load	62%
store	100%
mul	100%
add-sub	78%
fma	100%
div/sqrt	100%
other	31%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.50 cycles. At this rate:

14% of peak load performance is reached (14.30 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.72 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 422000

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D28, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MOVPRFX Z24, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SDIV Z24.D, P0/M, Z24.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	1-0.50
ADD Z25.D, Z3.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z26, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLS Z26.D, P0/M, Z24.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADD Z27.D, Z4.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z29, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z29.D, P0/M, Z27.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
ADD Z24.D, Z21.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD Z26.D, Z23.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z25.D, P0/M, Z25.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z30, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z30.D, P0/M, Z5.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z30.D}, P0/Z, [X8, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
MOVPRFX Z31, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z31.D, P0/M, Z6.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z31.D}, P0/Z, [X28, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
SXTW Z24.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL D28, D28, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
DUP Z28.D, Z28.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z28.D, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
MOVPRFX Z30, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z30.D, P0/M, Z6.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z30.D}, P0/Z, [X28, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
MAD Z24.D, P0/M, Z7.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
FADD Z30.D, Z31.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z31, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z31.D, P0/M, Z7.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z31.D}, P0/Z, [X23, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z24.D}, P0/Z, [X23, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z30.D, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FADD Z24.D, Z30.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z30, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z30.D, P0/M, Z30.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADR Z31.D, [Z30, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z30.D, [Z30, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z24.D, Z28.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
MOVPRFX Z28, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z28.D, P0/M, Z16.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ST1D {Z24.D}, P0, [X13, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
MOVPRFX Z28, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z28.D, P0/M, Z17.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LDR D24, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LD1D {Z28.D}, P0/Z, [X21, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z31.D}, P0/Z, [X22, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z30.D}, P0/Z, [X22, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z30.D, Z31.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z31, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z31.D, P0/M, Z31.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADR Z27.D, [Z31, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z26.D, [Z31, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MAD Z25.D, P0/M, Z20.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
FMUL D24, D24, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LD1D {Z27.D}, P0/Z, [X24, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z26.D}, P0/Z, [X24, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
DUP Z24.D, Z24.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FADD Z27.D, Z30.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z24.D, Z24.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FADD Z26.D, Z27.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z24.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
ST1D {Z24.D}, P0, [X25, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
B.NE 422000 <.omp_outlined.+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x421e30
Source file and lines	flux_calc.cpp:36-40
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/flux_calc.cpp:36-40

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

70% of VPU instructions are used in vector version (process two or more data elements in vector registers):

62% of VPU loads are used in vector version.
78% of VPU addition or subtraction instructions are used in vector version.
31% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 42 FP arithmetical operations:

24: addition or subtraction
18: multiply

The binary loop is loading 336 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	65
loop length	260
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	23.50	23.50	2.00	2.00	6.00	6.00	2.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	23.50	23.50	5.50	5.50	6.00	6.00	2.00	0.00	0.00

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.13
Data deps.	2.00
Overall L1	23.50

Vectorization ratios

INT

all	65%
load	62%
store	100%
mul	100%
add-sub	70%
fma	100%
other	35%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	70%
load	62%
store	100%
mul	100%
add-sub	78%
fma	100%
div/sqrt	100%
other	31%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.50 cycles. At this rate:

14% of peak load performance is reached (14.30 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.72 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 422000

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D28, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MOVPRFX Z24, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SDIV Z24.D, P0/M, Z24.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	1-0.50
ADD Z25.D, Z3.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z26, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLS Z26.D, P0/M, Z24.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADD Z27.D, Z4.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z29, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z29.D, P0/M, Z27.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SUBS X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
ADD Z24.D, Z21.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD Z26.D, Z23.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z25.D, P0/M, Z25.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z30, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z30.D, P0/M, Z5.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z30.D}, P0/Z, [X8, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
MOVPRFX Z31, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z31.D, P0/M, Z6.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z31.D}, P0/Z, [X28, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
SXTW Z24.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL D28, D28, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
DUP Z28.D, Z28.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z28.D, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
MOVPRFX Z30, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z30.D, P0/M, Z6.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z30.D}, P0/Z, [X28, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
MAD Z24.D, P0/M, Z7.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
FADD Z30.D, Z31.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z31, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z31.D, P0/M, Z7.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z31.D}, P0/Z, [X23, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z24.D}, P0/Z, [X23, Z24.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z30.D, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FADD Z24.D, Z30.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z30, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z30.D, P0/M, Z30.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADR Z31.D, [Z30, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z30.D, [Z30, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z24.D, Z28.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
MOVPRFX Z28, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z28.D, P0/M, Z16.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ST1D {Z24.D}, P0, [X13, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
MOVPRFX Z28, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MLA Z28.D, P0/M, Z17.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LDR D24, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LD1D {Z28.D}, P0/Z, [X21, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z31.D}, P0/Z, [X22, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z30.D}, P0/Z, [X22, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FADD Z30.D, Z31.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z31, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MUL Z31.D, P0/M, Z31.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ADR Z27.D, [Z31, Z27.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
ADR Z26.D, [Z31, Z26.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MAD Z25.D, P0/M, Z20.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
FMUL D24, D24, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LD1D {Z27.D}, P0/Z, [X24, Z27.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1D {Z26.D}, P0/Z, [X24, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
DUP Z24.D, Z24.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FADD Z27.D, Z30.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z24.D, Z24.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FADD Z26.D, Z27.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FMUL Z24.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
ST1D {Z24.D}, P0, [X25, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
B.NE 422000 <.omp_outlined.+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code