OV - exec - Loop 167

0x423400 MOVPRFX	Z0, Z16

0x423404 SDIV	Z0.D, P4/M, Z0.D, Z18.D

0x423408 ADD	Z1.D, Z19.D, Z0.D

0x42340c MSB	Z0.D, P4/M, Z18.D, Z16.D

0x423410 MOVPRFX	Z8, Z1

0x423414 SXTW	Z8.D, P4/M, Z1.D

0x423418 LDR	X8, [X20, #16]    [2]

0x42341c ORR	P0.B, P4/Z, P4.B, P4.B

0x423420 ADD	Z0.D, Z22.D, Z0.D

0x423424 MOVPRFX	Z23, Z0

0x423428 SXTW	Z23.D, P4/M, Z0.D

0x42342c LD1RD	{Z0.D}, P4/Z, [X20]    [2]

0x423430 MAD	Z0.D, P4/M, Z8.D, Z23.D

0x423434 LD1D	{Z1.D}, P4/Z, [X8, Z0.D,LSL #3]    [5]

0x423438 LD1RD	{Z3.D}, P4/Z, [X26]    [6]

0x42343c LDR	X9, [X26, #16]    [6]

0x423440 MOVPRFX	Z2, Z20

0x423444 FDIV	Z2.D, P4/M, Z2.D, Z1.D

0x423448 FMUL	Z2.D, Z2.D, Z2.D

0x42344c FMUL	Z1.D, Z1.D, Z21.D

0x423450 MAD	Z3.D, P4/M, Z8.D, Z23.D

0x423454 LD1D	{Z3.D}, P4/Z, [X9, Z3.D,LSL #3]    [3]

0x423458 LDR	X9, [X19, #16]    [7]

0x42345c FMUL	Z1.D, Z1.D, Z3.D

0x423460 LD1RD	{Z3.D}, P4/Z, [X19]    [7]

0x423464 MAD	Z3.D, P4/M, Z8.D, Z23.D

0x423468 ST1D	{Z1.D}, P4, [X9, Z3.D,LSL #3]    [4]

0x42346c LD1D	{Z0.D}, P4/Z, [X8, Z0.D,LSL #3]    [5]

0x423470 FMUL	Z3.D, Z0.D, Z21.D

0x423474 FMUL	Z0.D, Z1.D, Z0.D

0x423478 FMLA	Z0.D, P4/M, Z1.D, Z3.D

0x42347c FMUL	Z0.D, Z2.D, Z0.D

0x423480 BL	402eb0

0x423484 LD1RD	{Z1.D}, P4/Z, [X25]    [6]

0x423488 LDR	X8, [X25, #16]    [6]

0x42348c ADD	Z16.D, Z16.D, Z17.D

0x423490 SUBS	X21, X21, X24

0x423494 MAD	Z1.D, P4/M, Z8.D, Z23.D

0x423498 ST1D	{Z0.D}, P4, [X8, Z1.D,LSL #3]    [1]

0x42349c B.NE	423400

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/ideal_gas.cpp: 38 - 45

--------------------------------------------------------------------------------

38:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

39:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

40:       double v = 1.0 / density(i, j);

41:       pressure(i, j) = (1.4 - 1.0) * density(i, j) * energy(i, j);

42:       double pressurebyenergy = (1.4 - 1.0) * density(i, j);

43:       double pressurebyvolume = -density(i, j) * pressure(i, j);

44:       double sound_speed_squared = v * v * (pressure(i, j) * pressurebyenergy - pressurebyvolume);

45:       soundspeed(i, j) = std::sqrt(sound_speed_squared);

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.30
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x4232e0
Source	context.h:69-69,ideal_gas.cpp:38-45
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	11.50
CQA cycles if no scalar integer	11.50
CQA cycles if FP arith vectorized	11.50
CQA cycles if fully vectorized	11.50
Front-end cycles	5.00
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	1.00
P4 cycles	0.50
P5 cycles	11.50
P6 cycles	11.50
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	4.50
P10 cycles	4.50
P11 cycles	4.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00 - 1.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	40.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	3.13
Nb FLOP add-sub	0.00
Nb FLOP mul	24.00
Nb FLOP fma	4.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.48
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	75.76
Vectorization ratio load	42.86
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	42.86
Vector-efficiency ratio all	88.26
Vector-efficiency ratio load	57.14
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	87.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.30
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x4232e0
Source	context.h:69-69,ideal_gas.cpp:38-45
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	11.50
CQA cycles if no scalar integer	11.50
CQA cycles if FP arith vectorized	11.50
CQA cycles if fully vectorized	11.50
Front-end cycles	5.00
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	1.00
P4 cycles	0.50
P5 cycles	11.50
P6 cycles	11.50
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	4.50
P10 cycles	4.50
P11 cycles	4.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.00 - 1.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	40.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	3.13
Nb FLOP add-sub	0.00
Nb FLOP mul	24.00
Nb FLOP fma	4.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.48
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	75.76
Vectorization ratio load	42.86
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	42.86
Vector-efficiency ratio all	88.26
Vector-efficiency ratio load	57.14
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	87.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x4232e0
Source file and lines	ideal_gas.cpp:38-45
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/ideal_gas.cpp:38-45

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 88% of vector register length is used (average across all VPU instructions).

Details

75% of VPU instructions are used in vector version (process two or more data elements in vector registers):

42% of VPU loads are used in vector version.
42% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 11.50 to 2.00 cycles (5.75x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 36 FP arithmetical operations:

4: addition or subtraction (all inside FMA instructions)
28: multiply (4 inside FMA instructions)
4: divide

The binary loop is loading 160 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	0.75	0.75	1.00	0.50	11.50	11.50	1.00	1.00	4.50	4.50	4.00	0.00	0.00
cycles	1.00	1.00	0.75	0.75	1.00	0.50	11.50	11.50	3.50	3.50	4.50	4.50	4.00	0.00	0.00

Cycles executing div or sqrt instructions	2.00-1.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	5.00
Data deps.	2.00
Overall L1	11.50

Vectorization ratios

INT

all	68%
load	42%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
other	50%

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	75%
load	42%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	42%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.50 cycles. At this rate:

14% of peak load performance is reached (13.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (5.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 423400

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
MOVPRFX Z0, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SDIV Z0.D, P4/M, Z0.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	1-0.50
ADD Z1.D, Z19.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MSB Z0.D, P4/M, Z18.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
MOVPRFX Z8, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z8.D, P4/M, Z1.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
LDR X8, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR P0.B, P4/Z, P4.B, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1
ADD Z0.D, Z22.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z23, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z23.D, P4/M, Z0.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
LD1RD {Z0.D}, P4/Z, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
MAD Z0.D, P4/M, Z8.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z1.D}, P4/Z, [X8, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z3.D}, P4/Z, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LDR X9, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MOVPRFX Z2, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FDIV Z2.D, P4/M, Z2.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
FMUL Z2.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z1.D, Z1.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
MAD Z3.D, P4/M, Z8.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z3.D}, P4/Z, [X9, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LDR X9, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
FMUL Z1.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
LD1RD {Z3.D}, P4/Z, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
MAD Z3.D, P4/M, Z8.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ST1D {Z1.D}, P4, [X9, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
LD1D {Z0.D}, P4/Z, [X8, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FMUL Z3.D, Z0.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z0.D, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMLA Z0.D, P4/M, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FMUL Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
BL 402eb0 <@plt_start@+0x160>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LD1RD {Z1.D}, P4/Z, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LDR X8, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SUBS X21, X21, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
MAD Z1.D, P4/M, Z8.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ST1D {Z0.D}, P4, [X8, Z1.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
B.NE 423400 <.omp_outlined.+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x4232e0
Source file and lines	ideal_gas.cpp:38-45
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/ideal_gas.cpp:38-45

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 88% of vector register length is used (average across all VPU instructions).

Details

75% of VPU instructions are used in vector version (process two or more data elements in vector registers):

42% of VPU loads are used in vector version.
42% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 11.50 to 2.00 cycles (5.75x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 36 FP arithmetical operations:

4: addition or subtraction (all inside FMA instructions)
28: multiply (4 inside FMA instructions)
4: divide

The binary loop is loading 160 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	40
loop length	160
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	0.75	0.75	1.00	0.50	11.50	11.50	1.00	1.00	4.50	4.50	4.00	0.00	0.00
cycles	1.00	1.00	0.75	0.75	1.00	0.50	11.50	11.50	3.50	3.50	4.50	4.50	4.00	0.00	0.00

Cycles executing div or sqrt instructions	2.00-1.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	5.00
Data deps.	2.00
Overall L1	11.50

Vectorization ratios

INT

all	68%
load	42%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
other	50%

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	75%
load	42%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	42%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.50 cycles. At this rate:

14% of peak load performance is reached (13.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (5.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 423400

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
MOVPRFX Z0, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SDIV Z0.D, P4/M, Z0.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	1-0.50
ADD Z1.D, Z19.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MSB Z0.D, P4/M, Z18.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
MOVPRFX Z8, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z8.D, P4/M, Z1.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
LDR X8, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR P0.B, P4/Z, P4.B, P4.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1
ADD Z0.D, Z22.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MOVPRFX Z23, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SXTW Z23.D, P4/M, Z0.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1
LD1RD {Z0.D}, P4/Z, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
MAD Z0.D, P4/M, Z8.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z1.D}, P4/Z, [X8, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LD1RD {Z3.D}, P4/Z, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LDR X9, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MOVPRFX Z2, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FDIV Z2.D, P4/M, Z2.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	1-0.50
FMUL Z2.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z1.D, Z1.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
MAD Z3.D, P4/M, Z8.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
LD1D {Z3.D}, P4/Z, [X9, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LDR X9, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
FMUL Z1.D, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
LD1RD {Z3.D}, P4/Z, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
MAD Z3.D, P4/M, Z8.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ST1D {Z1.D}, P4, [X9, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
LD1D {Z0.D}, P4/Z, [X8, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
FMUL Z3.D, Z0.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMUL Z0.D, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
FMLA Z0.D, P4/M, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50
FMUL Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50
BL 402eb0 <@plt_start@+0x160>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LD1RD {Z1.D}, P4/Z, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50
LDR X8, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD Z16.D, Z16.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SUBS X21, X21, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
MAD Z1.D, P4/M, Z8.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2
ST1D {Z0.D}, P4, [X8, Z1.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	2	0.50
B.NE 423400 <.omp_outlined.+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code