OV - exec - Loop 159

	Loop Id: 159	Module: exec	Source: PdV.cpp:48-63 [...]	Coverage: 6.16%

0x4279e0 MOVPRFX	Z30, Z0

0x4279e4 SDIV	Z30.D, P0/M, Z30.D, Z2.D

0x4279e8 ADD	Z29.D, Z3.D, Z30.D

0x4279ec MOVPRFX	Z31, Z0

0x4279f0 MLS	Z31.D, P0/M, Z30.D, Z2.D

0x4279f4 ADD	Z8.D, Z4.D, Z31.D

0x4279f8 MOVPRFX	Z28, Z8

0x4279fc SXTW	Z28.D, P0/M, Z8.D

0x427a00 SUBS	X13, X13, X11

0x427a04 ADD	Z30.D, Z24.D, Z30.D

0x427a08 ADD	Z31.D, Z27.D, Z31.D

0x427a0c ADD	Z0.D, Z0.D, Z1.D

0x427a10 SXTW	Z29.D, P0/M, Z29.D

0x427a14 MOVPRFX	Z9, Z5

0x427a18 MUL	Z9.D, P0/M, Z9.D, Z29.D

0x427a1c MOVPRFX	Z11, Z6

0x427a20 MUL	Z11.D, P0/M, Z11.D, Z29.D

0x427a24 ADR	Z10.D, [Z9, Z8.D,SXTW]    [30]

0x427a28 LD1D	{Z10.D}, P0/Z, [X23, Z10.D,LSL #3]    [22]

0x427a2c ADR	Z12.D, [Z11, Z8.D,SXTW]    [28]

0x427a30 SXTW	Z30.D, P0/M, Z30.D

0x427a34 MOVPRFX	Z13, Z6

0x427a38 MUL	Z13.D, P0/M, Z13.D, Z30.D

0x427a3c ADR	Z14.D, [Z13, Z8.D,SXTW]    [18]

0x427a40 LD1D	{Z12.D}, P0/Z, [X25, Z12.D,LSL #3]    [11]

0x427a44 LD1D	{Z14.D}, P0/Z, [X25, Z14.D,LSL #3]    [24]

0x427a48 ADR	Z9.D, [Z9, Z31.D,SXTW]    [16]

0x427a4c ADR	Z11.D, [Z11, Z31.D,SXTW]    [13]

0x427a50 ADR	Z13.D, [Z13, Z31.D,SXTW]    [29]

0x427a54 FADD	Z15.D, Z12.D, Z14.D

0x427a58 FADD	Z12.D, Z12.D, Z15.D

0x427a5c FADD	Z12.D, Z14.D, Z12.D

0x427a60 FMUL	Z10.D, Z10.D, Z12.D

0x427a64 LD1RD	{Z12.D}, P0/Z, [X3]    [21]

0x427a68 LD1D	{Z9.D}, P0/Z, [X23, Z9.D,LSL #3]    [8]

0x427a6c LD1D	{Z11.D}, P0/Z, [X25, Z11.D,LSL #3]    [7]

0x427a70 LD1D	{Z13.D}, P0/Z, [X25, Z13.D,LSL #3]    [25]

0x427a74 FMUL	Z10.D, Z10.D, Z25.D

0x427a78 FADD	Z14.D, Z11.D, Z13.D

0x427a7c FADD	Z11.D, Z11.D, Z14.D

0x427a80 FMUL	Z10.D, Z12.D, Z10.D

0x427a84 FADD	Z11.D, Z13.D, Z11.D

0x427a88 MOVPRFX	Z13, Z16

0x427a8c MUL	Z13.D, P0/M, Z13.D, Z29.D

0x427a90 ADR	Z14.D, [Z13, Z8.D,SXTW]    [19]

0x427a94 ADR	Z13.D, [Z13, Z31.D,SXTW]    [14]

0x427a98 FMUL	Z10.D, P0/M, Z10.D, #0

0x427a9c FMUL	Z9.D, Z9.D, Z11.D

0x427aa0 MOVPRFX	Z11, Z28

0x427aa4 MLA	Z11.D, P0/M, Z7.D, Z29.D

0x427aa8 LD1D	{Z11.D}, P0/Z, [X27, Z11.D,LSL #3]    [17]

0x427aac LD1D	{Z14.D}, P0/Z, [X19, Z14.D,LSL #3]    [6]

0x427ab0 LD1D	{Z13.D}, P0/Z, [X19, Z13.D,LSL #3]    [20]

0x427ab4 FMUL	Z9.D, Z9.D, Z25.D

0x427ab8 FADD	Z15.D, Z14.D, Z13.D

0x427abc FADD	Z14.D, Z14.D, Z15.D

0x427ac0 FMUL	Z9.D, Z12.D, Z9.D

0x427ac4 FADD	Z13.D, Z13.D, Z14.D

0x427ac8 FMUL	Z9.D, P0/M, Z9.D, #0

0x427acc FMUL	Z11.D, Z11.D, Z13.D

0x427ad0 MOVPRFX	Z13, Z28

0x427ad4 MLA	Z13.D, P0/M, Z7.D, Z30.D

0x427ad8 MUL	Z30.D, P0/M, Z30.D, Z16.D

0x427adc LD1D	{Z13.D}, P0/Z, [X27, Z13.D,LSL #3]    [2]

0x427ae0 FMUL	Z11.D, Z11.D, Z25.D

0x427ae4 ADR	Z8.D, [Z30, Z8.D,SXTW]    [4]

0x427ae8 ADR	Z30.D, [Z30, Z31.D,SXTW]    [15]

0x427aec FMUL	Z31.D, Z12.D, Z11.D

0x427af0 LD1D	{Z8.D}, P0/Z, [X19, Z8.D,LSL #3]    [27]

0x427af4 LD1D	{Z30.D}, P0/Z, [X19, Z30.D,LSL #3]    [3]

0x427af8 FMUL	Z31.D, P0/M, Z31.D, #0

0x427afc FADD	Z11.D, Z8.D, Z30.D

0x427b00 FADD	Z8.D, Z8.D, Z11.D

0x427b04 FADD	Z30.D, Z30.D, Z8.D

0x427b08 FSUB	Z8.D, Z9.D, Z10.D

0x427b0c MOVPRFX	Z9, Z28

0x427b10 MLA	Z9.D, P0/M, Z18.D, Z29.D

0x427b14 MOVPRFX	Z10, Z28

0x427b18 MLA	Z10.D, P0/M, Z19.D, Z29.D

0x427b1c FMUL	Z30.D, Z13.D, Z30.D

0x427b20 MOVPRFX	Z13, Z28

0x427b24 MLA	Z13.D, P0/M, Z20.D, Z29.D

0x427b28 FMUL	Z30.D, Z30.D, Z25.D

0x427b2c FMUL	Z30.D, Z12.D, Z30.D

0x427b30 FMUL	Z30.D, P0/M, Z30.D, #0

0x427b34 FADD	Z30.D, Z8.D, Z30.D

0x427b38 FSUB	Z30.D, Z30.D, Z31.D

0x427b3c MOVPRFX	Z31, Z28

0x427b40 MLA	Z31.D, P0/M, Z17.D, Z29.D

0x427b44 LD1D	{Z31.D}, P0/Z, [X9, Z31.D,LSL #3]    [10]

0x427b48 LD1D	{Z9.D}, P0/Z, [X20, Z9.D,LSL #3]    [23]

0x427b4c LD1D	{Z11.D}, P0/Z, [X21, Z10.D,LSL #3]    [12]

0x427b50 LD1D	{Z13.D}, P0/Z, [X8, Z13.D,LSL #3]    [5]

0x427b54 MOVPRFX	Z8, Z26

0x427b58 FDIV	Z8.D, P0/M, Z8.D, Z31.D

0x427b5c FDIV	Z9.D, P0/M, Z9.D, Z11.D

0x427b60 FDIVR	Z11.D, P0/M, Z11.D, Z13.D

0x427b64 FADD	Z12.D, Z31.D, Z30.D

0x427b68 FDIV	Z31.D, P0/M, Z31.D, Z12.D

0x427b6c FADD	Z9.D, Z9.D, Z11.D

0x427b70 FMUL	Z30.D, Z9.D, Z30.D

0x427b74 FMUL	Z30.D, Z8.D, Z30.D

0x427b78 MOVPRFX	Z8, Z28

0x427b7c MLA	Z8.D, P0/M, Z21.D, Z29.D

0x427b80 LD1D	{Z8.D}, P0/Z, [X15, Z8.D,LSL #3]    [9]

0x427b84 FSUB	Z30.D, Z8.D, Z30.D

0x427b88 MOVPRFX	Z8, Z28

0x427b8c MLA	Z8.D, P0/M, Z22.D, Z29.D

0x427b90 MLA	Z28.D, P0/M, Z23.D, Z29.D

0x427b94 ST1D	{Z30.D}, P0, [X14, Z8.D,LSL #3]    [1]

0x427b98 LD1D	{Z30.D}, P0/Z, [X21, Z10.D,LSL #3]    [12]

0x427b9c FMUL	Z30.D, Z30.D, Z31.D

0x427ba0 ST1D	{Z30.D}, P0, [X16, Z28.D,LSL #3]    [26]

0x427ba4 B.NE	4279e0

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp: 48 - 63

--------------------------------------------------------------------------------

48: #pragma omp parallel for simd collapse(2)

49:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

50:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

51:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel0(i, j) + xvel0(i + 0, j + 1))) * 0.25 * dt * 0.5;

52:         double right_flux =

53:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1))) * 0.25 * dt *

54:             0.5;

55:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel0(i, j) + yvel0(i + 1, j + 0))) * 0.25 * dt * 0.5;

56:         double top_flux = (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1))) *

57:                           0.25 * dt * 0.5;

58:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

59:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

60:         double recip_volume = 1.0 / volume(i, j);

61:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

62:         energy1(i, j) = energy0(i, j) - energy_change;

63:         density1(i, j) = density0(i, j) * volume_change_s;

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.09
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.46
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x4277d0
Source	PdV.cpp:48-63,context.h:69-69
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	45.50
CQA cycles if no scalar integer	45.50
CQA cycles if FP arith vectorized	45.50
CQA cycles if fully vectorized	41.75
Front-end cycles	14.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	45.50
P6 cycles	45.50
P7 cycles	18.50
P8 cycles	18.50
P9 cycles	10.50
P10 cycles	10.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	5.00 - 2.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	114.00
Nb uops	114.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	3.60
Nb FLOP add-sub	72.00
Nb FLOP mul	76.00
Nb FLOP fma	0.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.24
Bytes prefetched	0.00
Bytes loaded	584.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	75.22
Vectorization ratio load	62.07
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	75.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	15.79
Vector-efficiency ratio all	92.04
Vector-efficiency ratio load	71.55
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	81.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.09
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.46
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x4277d0
Source	PdV.cpp:48-63,context.h:69-69
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	45.50
CQA cycles if no scalar integer	45.50
CQA cycles if FP arith vectorized	45.50
CQA cycles if fully vectorized	41.75
Front-end cycles	14.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	45.50
P6 cycles	45.50
P7 cycles	18.50
P8 cycles	18.50
P9 cycles	10.50
P10 cycles	10.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	5.00 - 2.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	114.00
Nb uops	114.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	3.60
Nb FLOP add-sub	72.00
Nb FLOP mul	76.00
Nb FLOP fma	0.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.24
Bytes prefetched	0.00
Bytes loaded	584.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	75.22
Vectorization ratio load	62.07
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	75.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	15.79
Vector-efficiency ratio all	92.04
Vector-efficiency ratio load	71.55
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	81.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x4277d0
Source file and lines	PdV.cpp:48-63
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:48-63
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 92% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 45.50 to 41.75 cycles (1.09x speedup).

Details

75% of VPU instructions are used in vector version (process two or more data elements in vector registers):

62% of VPU loads are used in vector version.
75% of VPU addition or subtraction instructions are used in vector version.
15% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 164 FP arithmetical operations:

72: addition or subtraction
76: multiply
16: divide

The binary loop is loading 584 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	114
loop length	456
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

14.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	45.50	45.50	1.00	1.00	10.50	10.50	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	45.50	45.50	18.50	18.50	10.50	10.50	0.00	0.00	0.00

Cycles executing div or sqrt instructions	5.00-2.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	14.25
Data deps.	2.00
Overall L1	45.50

Vectorization ratios

INT

all	61%
load	62%
store	100%
mul	100%
add-sub	57%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	75%
load	62%
store	100%
mul	100%
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 45.50 cycles. At this rate:

13% of peak load performance is reached (12.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.41 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4279e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z30, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z30.D, P0/M, Z30.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z29.D, Z3.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z31, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z31.D, P0/M, Z30.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z8.D, Z4.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z28, Z8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z28.D, P0/M, Z8.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SUBS X13, X13, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z30.D, Z24.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z31.D, Z27.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z29.D, P0/M, Z29.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z9, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z9.D, P0/M, Z9.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MOVPRFX Z11, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z11.D, P0/M, Z11.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z10.D, [Z9, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z10.D}, P0/Z, [X23, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z12.D, [Z11, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z30.D, P0/M, Z30.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z13, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z13.D, P0/M, Z13.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z14.D, [Z13, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z12.D}, P0/Z, [X25, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z14.D}, P0/Z, [X25, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z9.D, [Z9, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z11.D, [Z11, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z13.D, [Z13, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z15.D, Z12.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z12.D, Z12.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z12.D, Z14.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, Z10.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1RD {Z12.D}, P0/Z, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z9.D}, P0/Z, [X23, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z11.D}, P0/Z, [X25, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z13.D}, P0/Z, [X25, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z10.D, Z10.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z14.D, Z11.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z11.D, Z11.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, Z12.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z11.D, Z13.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z13, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z13.D, P0/M, Z13.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z14.D, [Z13, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z13.D, [Z13, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, P0/M, Z10.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z9.D, Z9.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z11, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z11.D, P0/M, Z7.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z11.D}, P0/Z, [X27, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z14.D}, P0/Z, [X19, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z13.D}, P0/Z, [X19, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z9.D, Z9.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z15.D, Z14.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z14.D, Z14.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z9.D, Z12.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z13.D, Z13.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z9.D, P0/M, Z9.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z11.D, Z11.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z13, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z13.D, P0/M, Z7.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MUL Z30.D, P0/M, Z30.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z13.D}, P0/Z, [X27, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z11.D, Z11.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADR Z8.D, [Z30, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z30.D, [Z30, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z31.D, Z12.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z8.D}, P0/Z, [X19, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z30.D}, P0/Z, [X19, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z31.D, P0/M, Z31.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z11.D, Z8.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z8.D, Z8.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z30.D, Z30.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z8.D, Z9.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z9, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z9.D, P0/M, Z18.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MOVPRFX Z10, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z10.D, P0/M, Z19.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMUL Z30.D, Z13.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z13, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z13.D, P0/M, Z20.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMUL Z30.D, Z30.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z30.D, Z12.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z30.D, P0/M, Z30.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z30.D, Z8.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z30.D, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z31, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z31.D, P0/M, Z17.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z31.D}, P0/Z, [X9, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z9.D}, P0/Z, [X20, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z11.D}, P0/Z, [X21, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z13.D}, P0/Z, [X8, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z8, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z8.D, P0/M, Z8.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIV Z9.D, P0/M, Z9.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z11.D, P0/M, Z11.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z12.D, Z31.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z31.D, P0/M, Z31.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z9.D, Z9.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z30.D, Z9.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z30.D, Z8.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z8, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z8.D, P0/M, Z21.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z8.D}, P0/Z, [X15, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z30.D, Z8.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z8, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z8.D, P0/M, Z22.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MLA Z28.D, P0/M, Z23.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z30.D}, P0, [X14, Z8.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z30.D}, P0/Z, [X21, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z30.D, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z30.D}, P0, [X16, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 4279e0 <.omp_outlined.+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x4277d0
Source file and lines	PdV.cpp:48-63
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:48-63
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

75% of VPU instructions are used in vector version (process two or more data elements in vector registers):

62% of VPU loads are used in vector version.
75% of VPU addition or subtraction instructions are used in vector version.
15% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 164 FP arithmetical operations:

72: addition or subtraction
76: multiply
16: divide

The binary loop is loading 584 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	114
loop length	456
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

14.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	45.50	45.50	1.00	1.00	10.50	10.50	0.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	45.50	45.50	18.50	18.50	10.50	10.50	0.00	0.00	0.00

Cycles executing div or sqrt instructions	5.00-2.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	14.25
Data deps.	2.00
Overall L1	45.50

Vectorization ratios

INT

all	61%
load	62%
store	100%
mul	100%
add-sub	57%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	75%
load	62%
store	100%
mul	100%
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 45.50 cycles. At this rate:

13% of peak load performance is reached (12.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.41 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4279e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z30, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z30.D, P0/M, Z30.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
ADD Z29.D, Z3.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z31, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z31.D, P0/M, Z30.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z8.D, Z4.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z28, Z8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z28.D, P0/M, Z8.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
SUBS X13, X13, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z30.D, Z24.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z31.D, Z27.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z29.D, P0/M, Z29.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z9, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z9.D, P0/M, Z9.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MOVPRFX Z11, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z11.D, P0/M, Z11.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z10.D, [Z9, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z10.D}, P0/Z, [X23, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z12.D, [Z11, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z30.D, P0/M, Z30.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z13, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z13.D, P0/M, Z13.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z14.D, [Z13, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z12.D}, P0/Z, [X25, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z14.D}, P0/Z, [X25, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z9.D, [Z9, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z11.D, [Z11, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z13.D, [Z13, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z15.D, Z12.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z12.D, Z12.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z12.D, Z14.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, Z10.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1RD {Z12.D}, P0/Z, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z9.D}, P0/Z, [X23, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z11.D}, P0/Z, [X25, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z13.D}, P0/Z, [X25, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z10.D, Z10.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z14.D, Z11.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z11.D, Z11.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, Z12.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z11.D, Z13.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z13, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z13.D, P0/M, Z13.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z14.D, [Z13, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z13.D, [Z13, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, P0/M, Z10.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z9.D, Z9.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z11, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z11.D, P0/M, Z7.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z11.D}, P0/Z, [X27, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z14.D}, P0/Z, [X19, Z14.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z13.D}, P0/Z, [X19, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z9.D, Z9.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z15.D, Z14.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z14.D, Z14.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z9.D, Z12.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z13.D, Z13.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z9.D, P0/M, Z9.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z11.D, Z11.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z13, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z13.D, P0/M, Z7.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MUL Z30.D, P0/M, Z30.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z13.D}, P0/Z, [X27, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z11.D, Z11.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADR Z8.D, [Z30, Z8.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z30.D, [Z30, Z31.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z31.D, Z12.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z8.D}, P0/Z, [X19, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z30.D}, P0/Z, [X19, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z31.D, P0/M, Z31.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z11.D, Z8.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z8.D, Z8.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z30.D, Z30.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z8.D, Z9.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z9, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z9.D, P0/M, Z18.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MOVPRFX Z10, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z10.D, P0/M, Z19.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMUL Z30.D, Z13.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z13, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z13.D, P0/M, Z20.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMUL Z30.D, Z30.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z30.D, Z12.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z30.D, P0/M, Z30.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z30.D, Z8.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z30.D, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z31, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z31.D, P0/M, Z17.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z31.D}, P0/Z, [X9, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z9.D}, P0/Z, [X20, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z11.D}, P0/Z, [X21, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z13.D}, P0/Z, [X8, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z8, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z8.D, P0/M, Z8.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIV Z9.D, P0/M, Z9.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z11.D, P0/M, Z11.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z12.D, Z31.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z31.D, P0/M, Z31.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z9.D, Z9.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z30.D, Z9.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z30.D, Z8.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z8, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z8.D, P0/M, Z21.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z8.D}, P0/Z, [X15, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z30.D, Z8.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z8, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z8.D, P0/M, Z22.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MLA Z28.D, P0/M, Z23.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ST1D {Z30.D}, P0, [X14, Z8.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z30.D}, P0/Z, [X21, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z30.D, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z30.D}, P0, [X16, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
B.NE 4279e0 <.omp_outlined.+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code