OV - exec - Loop 146

	Loop Id: 146	Module: exec	Source: viscosity.cpp:37-64 [...]	Coverage: 2.68%

0x43de00 MOVPRFX	Z26, Z0

0x43de04 SDIV	Z26.D, P0/M, Z26.D, Z2.D

0x43de08 MOVPRFX	Z28, Z0

0x43de0c MLS	Z28.D, P0/M, Z26.D, Z2.D

0x43de10 ADD	Z29.D, Z4.D, Z28.D

0x43de14 ADD	Z30.D, Z20.D, Z28.D

0x43de18 SUB	X17, X29, #64

0x43de1c SUBS	X5, X5, X3

0x43de20 ADD	Z9.D, Z21.D, Z26.D

0x43de24 ADD	Z27.D, Z3.D, Z26.D

0x43de28 MOVPRFX	Z25, Z27

0x43de2c SXTW	Z25.D, P0/M, Z27.D

0x43de30 MOVPRFX	Z31, Z5

0x43de34 MUL	Z31.D, P0/M, Z31.D, Z25.D

0x43de38 MOVPRFX	Z15, Z6

0x43de3c MUL	Z15.D, P0/M, Z15.D, Z25.D

0x43de40 ADD	Z28.D, Z16.D, Z28.D

0x43de44 ADR	Z8.D, [Z31, Z30.D,SXTW]    [25]

0x43de48 LD1D	{Z8.D}, P0/Z, [X8, Z8.D,LSL #3]    [23]

0x43de4c SXTW	Z9.D, P0/M, Z9.D

0x43de50 MOVPRFX	Z10, Z5

0x43de54 MUL	Z10.D, P0/M, Z10.D, Z9.D

0x43de58 ADR	Z11.D, [Z10, Z30.D,SXTW]    [24]

0x43de5c ADR	Z31.D, [Z31, Z29.D,SXTW]    [10]

0x43de60 ADR	Z10.D, [Z10, Z29.D,SXTW]    [15]

0x43de64 MOVPRFX	Z12, Z6

0x43de68 MUL	Z12.D, P0/M, Z12.D, Z9.D

0x43de6c LD1D	{Z11.D}, P0/Z, [X8, Z11.D,LSL #3]    [27]

0x43de70 LD1D	{Z31.D}, P0/Z, [X8, Z31.D,LSL #3]    [9]

0x43de74 LD1D	{Z10.D}, P0/Z, [X8, Z10.D,LSL #3]    [2]

0x43de78 ADR	Z13.D, [Z12, Z29.D,SXTW]    [3]

0x43de7c LD1D	{Z13.D}, P0/Z, [X10, Z13.D,LSL #3]    [8]

0x43de80 ADR	Z12.D, [Z12, Z30.D,SXTW]    [14]

0x43de84 LD1D	{Z12.D}, P0/Z, [X10, Z12.D,LSL #3]    [26]

0x43de88 ADR	Z23.D, [Z15, Z29.D,SXTW]    [4]

0x43de8c LD1D	{Z23.D}, P0/Z, [X10, Z23.D,LSL #3]    [13]

0x43de90 ADR	Z15.D, [Z15, Z30.D,SXTW]    [21]

0x43de94 LD1D	{Z15.D}, P0/Z, [X10, Z15.D,LSL #3]    [6]

0x43de98 FADD	Z14.D, Z13.D, Z12.D

0x43de9c FADD	Z1.D, Z23.D, Z15.D

0x43dea0 FSUB	Z1.D, Z14.D, Z1.D

0x43dea4 FADD	Z14.D, Z8.D, Z11.D

0x43dea8 FADD	Z11.D, Z11.D, Z10.D

0x43deac FSUB	Z11.D, Z11.D, Z31.D

0x43deb0 FADD	Z31.D, Z31.D, Z10.D

0x43deb4 MOVPRFX	Z10, Z7

0x43deb8 MUL	Z10.D, P0/M, Z10.D, Z25.D

0x43debc ADR	Z28.D, [Z10, Z28.D,SXTW]    [1]

0x43dec0 ADR	Z10.D, [Z10, Z30.D,SXTW]    [17]

0x43dec4 FSUB	Z8.D, Z11.D, Z8.D

0x43dec8 FADD	Z11.D, Z12.D, Z15.D

0x43decc FSUB	Z31.D, Z14.D, Z31.D

0x43ded0 FSUB	Z23.D, Z11.D, Z23.D

0x43ded4 LD1D	{Z11.D}, P0/Z, [X12, Z29.D,SXTW #3]    [5]

0x43ded8 LD1D	{Z27.D}, P0/Z, [X13, Z27.D,SXTW #3]    [29]

0x43dedc LD1D	{Z10.D}, P0/Z, [X14, Z10.D,LSL #3]    [28]

0x43dee0 LD1D	{Z28.D}, P0/Z, [X14, Z28.D,LSL #3]    [20]

0x43dee4 LD1D	{Z30.D}, P0/Z, [X12, Z30.D,SXTW #3]    [16]

0x43dee8 SXTW	Z29.D, P0/M, Z29.D

0x43deec FMUL	Z8.D, P0/M, Z8.D, #0

0x43def0 FSUB	Z23.D, Z23.D, Z13.D

0x43def4 FSUB	Z28.D, Z10.D, Z28.D

0x43def8 FADD	Z30.D, Z11.D, Z30.D

0x43defc FMUL	Z23.D, P0/M, Z23.D, #0

0x43df00 FDIV	Z8.D, P0/M, Z8.D, Z27.D

0x43df04 MOVPRFX	Z10, Z1

0x43df08 FMUL	Z10.D, P0/M, Z10.D, #0

0x43df0c FDIV	Z10.D, P0/M, Z10.D, Z27.D

0x43df10 FMUL	Z1.D, Z1.D, Z27.D

0x43df14 FDIV	Z28.D, P0/M, Z28.D, Z30.D

0x43df18 MOVPRFX	Z30, Z29

0x43df1c MLA	Z30.D, P0/M, Z7.D, Z9.D

0x43df20 ADD	Z9.D, Z17.D, Z26.D

0x43df24 ADD	Z26.D, Z24.D, Z26.D

0x43df28 LD1D	{Z30.D}, P0/Z, [X14, Z30.D,LSL #3]    [19]

0x43df2c FDIV	Z23.D, P0/M, Z23.D, Z11.D

0x43df30 FMLA	Z1.D, P0/M, Z11.D, Z31.D

0x43df34 SXTW	Z9.D, P0/M, Z9.D

0x43df38 MAD	Z9.D, P0/M, Z7.D, Z29.D

0x43df3c FCMGE	P2.D, P0/Z, Z1.D, #0

0x43df40 LD1D	{Z9.D}, P0/Z, [X14, Z9.D,LSL #3]    [18]

0x43df44 LD1D	{Z26.D}, P0/Z, [X13, Z26.D,SXTW #3]    [11]

0x43df48 FSUB	Z30.D, Z30.D, Z9.D

0x43df4c FADD	Z26.D, Z27.D, Z26.D

0x43df50 FDIVR	Z26.D, P0/M, Z26.D, Z30.D

0x43df54 FMUL	Z30.D, Z28.D, Z28.D

0x43df58 FCMLT	P1.D, P0/Z, Z28.D, #0

0x43df5c MOVPRFX	Z1, Z26

0x43df60 FABS	Z1.D, P0/M, Z26.D

0x43df64 FMAXNM	Z1.D, P0/M, Z1.D, Z22.D

0x43df68 FADD	Z23.D, Z8.D, Z23.D

0x43df6c MOVPRFX	Z8, Z31

0x43df70 FMUL	Z8.D, P0/M, Z8.D, #0

0x43df74 FDIV	Z8.D, P0/M, Z8.D, Z11.D

0x43df78 FMUL	Z23.D, Z23.D, Z28.D

0x43df7c FABS	Z28.D, P0/M, Z28.D

0x43df80 FMAXNM	Z28.D, P0/M, Z28.D, Z22.D

0x43df84 FMUL	Z9.D, Z26.D, Z26.D

0x43df88 FMUL	Z10.D, Z10.D, Z9.D

0x43df8c FMAD	Z8.D, P0/M, Z30.D, Z10.D

0x43df90 FADD	Z30.D, Z30.D, Z9.D

0x43df94 FMAXNM	Z30.D, P0/M, Z30.D, Z22.D

0x43df98 FMAD	Z23.D, P0/M, Z26.D, Z8.D

0x43df9c MOVPRFX	Z26, Z1

0x43dfa0 FNEG	Z26.D, P0/M, Z1.D

0x43dfa4 FDIV	Z23.D, P0/M, Z23.D, Z30.D

0x43dfa8 MOVPRFX	Z30, Z28

0x43dfac FNEG	Z30.D, P0/M, Z28.D

0x43dfb0 SEL	Z28.D, P1, Z30.D, Z28.D

0x43dfb4 FCMLT	P1.D, P0/Z, Z28.D, #0

0x43dfb8 SEL	Z1.D, P1, Z26.D, Z1.D

0x43dfbc FMUL	Z26.D, Z1.D, Z1.D

0x43dfc0 FMLA	Z26.D, P0/M, Z28.D, Z28.D

0x43dfc4 FSQRT	Z26.D, P0/M, Z26.D

0x43dfc8 FCMGT	P1.D, P0/Z, Z23.D, #0

0x43dfcc EOR	P1.B, P0/Z, P1.B, P0.B

0x43dfd0 BIC	P1.B, P1/Z, P1.B, P2.B

0x43dfd4 FMUL	Z30.D, Z11.D, Z26.D

0x43dfd8 FMUL	Z26.D, Z27.D, Z26.D

0x43dfdc MOVPRFX	Z27, Z30

0x43dfe0 FDIV	Z27.D, P0/M, Z27.D, Z28.D

0x43dfe4 FDIVR	Z1.D, P0/M, Z1.D, Z26.D

0x43dfe8 MOVPRFX	Z26, Z27

0x43dfec FABS	Z26.D, P0/M, Z27.D

0x43dff0 FABS	Z1.D, P0/M, Z1.D

0x43dff4 FMINNM	Z1.D, P0/M, Z1.D, Z26.D

0x43dff8 MOVPRFX	Z26, Z29

0x43dffc MLA	Z26.D, P0/M, Z18.D, Z25.D

0x43e000 LD1D	{Z26.D}, P1/Z, [X16, Z26.D,LSL #3]    [12]

0x43e004 FMUL	Z1.D, Z1.D, Z1.D

0x43e008 FADD	Z26.D, Z26.D, Z26.D

0x43e00c FMUL	Z1.D, Z1.D, Z26.D

0x43e010 FMUL	Z1.D, Z23.D, Z1.D

0x43e014 FMUL	Z1.D, Z23.D, Z1.D

0x43e018 DUP	Z23.D, #0

0x43e01c SEL	Z1.D, P1, Z1.D, Z23.D

0x43e020 MOVPRFX	Z23, Z29

0x43e024 MLA	Z23.D, P0/M, Z19.D, Z25.D

0x43e028 LDR	Z25, [X17, #511, MUL VL]    [22]

0x43e02c ST1D	{Z1.D}, P0, [X0, Z23.D,LSL #3]    [7]

0x43e030 ADD	Z0.D, Z0.D, Z25.D

0x43e034 B.NE	43de00

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp: 37 - 64

--------------------------------------------------------------------------------

37:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

39:       double ugrad = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) - (xvel0(i, j) + xvel0(i + 0, j + 1));

40:       double vgrad = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) - (yvel0(i, j) + yvel0(i + 1, j + 0));

41:       double div = (celldx[i] * (ugrad) + celldy[j] * (vgrad));

42:       double strain2 = 0.5 * (xvel0(i + 0, j + 1) + xvel0(i + 1, j + 1) - xvel0(i, j) - xvel0(i + 1, j + 0)) / celldy[j] +

43:                        0.5 * (yvel0(i + 1, j + 0) + yvel0(i + 1, j + 1) - yvel0(i, j) - yvel0(i + 0, j + 1)) / celldx[i];

44:       double pgradx = (pressure(i + 1, j + 0) - pressure(i - 1, j + 0)) / (celldx[i] + celldx[i + 1]);

45:       double pgrady = (pressure(i + 0, j + 1) - pressure(i + 0, j - 1)) / (celldy[j] + celldy[j + 2]);

46:       double pgradx2 = pgradx * pgradx;

47:       double pgrady2 = pgrady * pgrady;

48:       double limiter = ((0.5 * (ugrad) / celldx[i]) * pgradx2 + (0.5 * (vgrad) / celldy[j]) * pgrady2 + strain2 * pgradx * pgrady) /

49:                        std::fmax(pgradx2 + pgrady2, g_small);

50:       if ((limiter > 0.0) || (div >= 0.0)) {

51:         viscosity(i, j) = 0.0;

52:       } else {

53:         double dirx = 1.0;

54:         if (pgradx < 0.0) dirx = -1.0;

55:         pgradx = dirx * std::fmax(g_small, std::fabs(pgradx));

56:         double diry = 1.0;

57:         if (pgradx < 0.0) diry = -1.0;

58:         pgrady = diry * std::fmax(g_small, std::fabs(pgrady));

59:         double pgrad = std::sqrt(pgradx * pgradx + pgrady * pgrady);

60:         double xgrad = std::fabs(celldx[i] * pgrad / pgradx);

61:         double ygrad = std::fabs(celldy[j] * pgrad / pgrady);

62:         double grad = std::fmin(xgrad, ygrad);

63:         double grad2 = grad * grad;

64:         viscosity(i, j) = 2.0 * density0(i, j) * grad2 * limiter * limiter;

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.03
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x43dc40
Source	viscosity.cpp:37-64,context.h:69-69
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	59.00
CQA cycles if no scalar integer	59.00
CQA cycles if FP arith vectorized	59.00
CQA cycles if fully vectorized	54.77
Front-end cycles	17.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	2.00
P4 cycles	0.50
P5 cycles	59.00
P6 cycles	59.00
P7 cycles	19.50
P8 cycles	19.50
P9 cycles	9.50
P10 cycles	9.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	11.00 - 5.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	142.00
Nb uops	142.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	3.59
Nb FLOP add-sub	76.00
Nb FLOP mul	64.00
Nb FLOP fma	16.00
Nb FLOP div	36.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.31
Bytes prefetched	0.00
Bytes loaded	576.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	78.57
Vectorization ratio load	64.29
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	73.81
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	54.76
Vector-efficiency ratio all	92.17
Vector-efficiency ratio load	73.21
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	80.36
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	93.53

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.03
Bottlenecks	P6, P7,
Function	.omp_outlined.#0x43dc40
Source	viscosity.cpp:37-64,context.h:69-69
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	59.00
CQA cycles if no scalar integer	59.00
CQA cycles if FP arith vectorized	59.00
CQA cycles if fully vectorized	54.77
Front-end cycles	17.75
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	2.00
P4 cycles	0.50
P5 cycles	59.00
P6 cycles	59.00
P7 cycles	19.50
P8 cycles	19.50
P9 cycles	9.50
P10 cycles	9.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	11.00 - 5.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	142.00
Nb uops	142.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	3.59
Nb FLOP add-sub	76.00
Nb FLOP mul	64.00
Nb FLOP fma	16.00
Nb FLOP div	36.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.31
Bytes prefetched	0.00
Bytes loaded	576.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	78.57
Vectorization ratio load	64.29
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	73.81
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	54.76
Vector-efficiency ratio all	92.17
Vector-efficiency ratio load	73.21
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	80.36
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	93.53

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x43dc40
Source file and lines	viscosity.cpp:37-64
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp:37-64
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 92% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 59.00 to 54.77 cycles (1.08x speedup).

Details

78% of VPU instructions are used in vector version (process two or more data elements in vector registers):

64% of VPU loads are used in vector version.
73% of VPU addition or subtraction instructions are used in vector version.
54% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 212 FP arithmetical operations:

92: addition or subtraction (16 inside FMA instructions)
80: multiply (16 inside FMA instructions)
36: divide
4: square root

The binary loop is loading 576 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.35 FP operations per loaded or stored byte.

General properties

nb instructions	142
loop length	568
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	2.00	0.50	59.00	59.00	0.50	0.50	9.50	9.50	0.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	2.00	0.50	59.00	59.00	19.50	19.50	9.50	9.50	0.00	0.00	0.00

Cycles executing div or sqrt instructions	11.00-5.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	17.75
Data deps.	1.00
Overall L1	59.00

Vectorization ratios

INT

all	61%
load	64%
store	100%
mul	100%
add-sub	52%
fma	100%
other	34%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	78%
load	64%
store	100%
mul	100%
add-sub	73%
fma	100%
div/sqrt	100%
other	54%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 59.00 cycles. At this rate:

10% of peak load performance is reached (9.76 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.54 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43de00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z26, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z26.D, P0/M, Z26.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z28, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z28.D, P0/M, Z26.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z29.D, Z4.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z30.D, Z20.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUB X17, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUBS X5, X5, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z9.D, Z21.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z27.D, Z3.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z25, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z25.D, P0/M, Z27.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z31, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z31.D, P0/M, Z31.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MOVPRFX Z15, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z15.D, P0/M, Z15.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z28.D, Z16.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z8.D, [Z31, Z30.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z8.D}, P0/Z, [X8, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SXTW Z9.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z10, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z10.D, P0/M, Z10.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z11.D, [Z10, Z30.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z31.D, [Z31, Z29.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z10.D, [Z10, Z29.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z12, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z12.D, P0/M, Z12.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z11.D}, P0/Z, [X8, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X8, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P0/Z, [X8, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z13.D, [Z12, Z29.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z13.D}, P0/Z, [X10, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z12.D, [Z12, Z30.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z12.D}, P0/Z, [X10, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z23.D, [Z15, Z29.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z23.D}, P0/Z, [X10, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z15.D, [Z15, Z30.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z15.D}, P0/Z, [X10, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z14.D, Z13.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z1.D, Z23.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z1.D, Z14.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z14.D, Z8.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z11.D, Z11.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z11.D, Z11.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z31.D, Z31.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z10, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z10.D, P0/M, Z10.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z28.D, [Z10, Z28.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z10.D, [Z10, Z30.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z8.D, Z11.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z11.D, Z12.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z31.D, Z14.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z23.D, Z11.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z11.D}, P0/Z, [X12, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z27.D}, P0/Z, [X13, Z27.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P0/Z, [X14, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P0/Z, [X14, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z30.D}, P0/Z, [X12, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SXTW Z29.D, P0/M, Z29.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
FMUL Z8.D, P0/M, Z8.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z23.D, Z23.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z28.D, Z10.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z30.D, Z11.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, P0/M, Z23.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z8.D, P0/M, Z8.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z10, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, P0/M, Z10.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z10.D, P0/M, Z10.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z1.D, Z1.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z28.D, P0/M, Z28.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z30, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z30.D, P0/M, Z7.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z9.D, Z17.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z26.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z30.D}, P0/Z, [X14, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z23.D, P0/M, Z23.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMLA Z1.D, P0/M, Z11.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
SXTW Z9.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MAD Z9.D, P0/M, Z7.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FCMGE P2.D, P0/Z, Z1.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
LD1D {Z9.D}, P0/Z, [X14, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P0/Z, [X13, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z30.D, Z30.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z26.D, Z27.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIVR Z26.D, P0/M, Z26.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z30.D, Z28.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FCMLT P1.D, P0/Z, Z28.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z1, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z1.D, P0/M, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAXNM Z1.D, P0/M, Z1.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z23.D, Z8.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z8, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z8.D, P0/M, Z8.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z8.D, P0/M, Z8.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z23.D, Z23.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FABS Z28.D, P0/M, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAXNM Z28.D, P0/M, Z28.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z9.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z10.D, Z10.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z8.D, P0/M, Z30.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z30.D, Z30.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAXNM Z30.D, P0/M, Z30.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z23.D, P0/M, Z26.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z26, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z26.D, P0/M, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z23.D, P0/M, Z23.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z30, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z30.D, P0/M, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z28.D, P1, Z30.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMLT P1.D, P0/Z, Z28.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SEL Z1.D, P1, Z26.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z26.D, Z1.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z26.D, P0/M, Z28.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FSQRT Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	1-0.50
FCMGT P1.D, P0/Z, Z23.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
EOR P1.B, P0/Z, P1.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
BIC P1.B, P1/Z, P1.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
FMUL Z30.D, Z11.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z26.D, Z27.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z27, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z27.D, P0/M, Z27.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z1.D, P0/M, Z1.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z26, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z26.D, P0/M, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z1.D, P0/M, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z1.D, P0/M, Z1.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z26, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z26.D, P0/M, Z18.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z26.D}, P1/Z, [X16, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z1.D, Z1.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z1.D, Z1.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z1.D, Z23.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z1.D, Z23.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
DUP Z23.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z1.D, P1, Z1.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z23, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z23.D, P0/M, Z19.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LDR Z25, [X17, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z1.D}, P0, [X0, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD Z0.D, Z0.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
B.NE 43de00 <.omp_outlined.+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x43dc40
Source file and lines	viscosity.cpp:37-64
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp:37-64
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

78% of VPU instructions are used in vector version (process two or more data elements in vector registers):

64% of VPU loads are used in vector version.
73% of VPU addition or subtraction instructions are used in vector version.
54% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 212 FP arithmetical operations:

92: addition or subtraction (16 inside FMA instructions)
80: multiply (16 inside FMA instructions)
36: divide
4: square root

The binary loop is loading 576 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.35 FP operations per loaded or stored byte.

General properties

nb instructions	142
loop length	568
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	2.00	0.50	59.00	59.00	0.50	0.50	9.50	9.50	0.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	2.00	0.50	59.00	59.00	19.50	19.50	9.50	9.50	0.00	0.00	0.00

Cycles executing div or sqrt instructions	11.00-5.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	17.75
Data deps.	1.00
Overall L1	59.00

Vectorization ratios

INT

all	61%
load	64%
store	100%
mul	100%
add-sub	52%
fma	100%
other	34%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	78%
load	64%
store	100%
mul	100%
add-sub	73%
fma	100%
div/sqrt	100%
other	54%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 59.00 cycles. At this rate:

10% of peak load performance is reached (9.76 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.54 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43de00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVPRFX Z26, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SDIV Z26.D, P0/M, Z26.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	1-0.50
MOVPRFX Z28, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLS Z28.D, P0/M, Z26.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z29.D, Z4.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z30.D, Z20.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUB X17, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUBS X5, X5, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
ADD Z9.D, Z21.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z27.D, Z3.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z25, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SXTW Z25.D, P0/M, Z27.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z31, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z31.D, P0/M, Z31.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
MOVPRFX Z15, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z15.D, P0/M, Z15.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z28.D, Z16.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z8.D, [Z31, Z30.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z8.D}, P0/Z, [X8, Z8.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SXTW Z9.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MOVPRFX Z10, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z10.D, P0/M, Z10.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z11.D, [Z10, Z30.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z31.D, [Z31, Z29.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z10.D, [Z10, Z29.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z12, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z12.D, P0/M, Z12.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z11.D}, P0/Z, [X8, Z11.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X8, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P0/Z, [X8, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z13.D, [Z12, Z29.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z13.D}, P0/Z, [X10, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z12.D, [Z12, Z30.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z12.D}, P0/Z, [X10, Z12.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z23.D, [Z15, Z29.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z23.D}, P0/Z, [X10, Z23.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADR Z15.D, [Z15, Z30.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z15.D}, P0/Z, [X10, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z14.D, Z13.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z1.D, Z23.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z1.D, Z14.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z14.D, Z8.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z11.D, Z11.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z11.D, Z11.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z31.D, Z31.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z10, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MUL Z10.D, P0/M, Z10.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADR Z28.D, [Z10, Z28.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADR Z10.D, [Z10, Z30.D,SXTW]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z8.D, Z11.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z11.D, Z12.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z31.D, Z14.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z23.D, Z11.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z11.D}, P0/Z, [X12, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z27.D}, P0/Z, [X13, Z27.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z10.D}, P0/Z, [X14, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z28.D}, P0/Z, [X14, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z30.D}, P0/Z, [X12, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SXTW Z29.D, P0/M, Z29.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
FMUL Z8.D, P0/M, Z8.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z23.D, Z23.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z28.D, Z10.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z30.D, Z11.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, P0/M, Z23.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z8.D, P0/M, Z8.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z10, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, P0/M, Z10.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z10.D, P0/M, Z10.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z1.D, Z1.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z28.D, P0/M, Z28.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z30, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z30.D, P0/M, Z7.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
ADD Z9.D, Z17.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z26.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z30.D}, P0/Z, [X14, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z23.D, P0/M, Z23.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMLA Z1.D, P0/M, Z11.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
SXTW Z9.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1
MAD Z9.D, P0/M, Z7.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FCMGE P2.D, P0/Z, Z1.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
LD1D {Z9.D}, P0/Z, [X14, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P0/Z, [X13, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z30.D, Z30.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z26.D, Z27.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIVR Z26.D, P0/M, Z26.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z30.D, Z28.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FCMLT P1.D, P0/Z, Z28.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z1, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z1.D, P0/M, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAXNM Z1.D, P0/M, Z1.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z23.D, Z8.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z8, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z8.D, P0/M, Z8.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z8.D, P0/M, Z8.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z23.D, Z23.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FABS Z28.D, P0/M, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAXNM Z28.D, P0/M, Z28.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z9.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z10.D, Z10.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z8.D, P0/M, Z30.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FADD Z30.D, Z30.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAXNM Z30.D, P0/M, Z30.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z23.D, P0/M, Z26.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
MOVPRFX Z26, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z26.D, P0/M, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z23.D, P0/M, Z23.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z30, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNEG Z30.D, P0/M, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z28.D, P1, Z30.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMLT P1.D, P0/Z, Z28.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SEL Z1.D, P1, Z26.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z26.D, Z1.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z26.D, P0/M, Z28.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FSQRT Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-16	1-0.50
FCMGT P1.D, P0/Z, Z23.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
EOR P1.B, P0/Z, P1.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
BIC P1.B, P1/Z, P1.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
FMUL Z30.D, Z11.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z26.D, Z27.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z27, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z27.D, P0/M, Z27.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z1.D, P0/M, Z1.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MOVPRFX Z26, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z26.D, P0/M, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z1.D, P0/M, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z1.D, P0/M, Z1.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z26, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z26.D, P0/M, Z18.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z26.D}, P1/Z, [X16, Z26.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z1.D, Z1.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z26.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z1.D, Z1.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z1.D, Z23.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z1.D, Z23.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
DUP Z23.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z1.D, P1, Z1.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z23, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z23.D, P0/M, Z19.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LDR Z25, [X17, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ST1D {Z1.D}, P0, [X0, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD Z0.D, Z0.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
B.NE 43de00 <.omp_outlined.+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code