OV - exec - Function .omp_outlined..22#0x42bbc0

	Function: .omp_outlined..22#0x42bbc0	Module: exec	Source: update_halo.cpp:160-163 [...]	Coverage: 0.01%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 160 - 163

--------------------------------------------------------------------------------

160: #pragma omp parallel for simd

161:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

162:         for (int j = 0; j < depth; ++j) {

163:           field.energy0(x_max + 2 + j, k) = field.energy0(x_max + 1 - j, k);

0x42bbc0 SUB	SP, SP, #144

0x42bbc4 STP	X29, X30, [SP, #48]

0x42bbc8 STP	X28, X27, [SP, #64]

0x42bbcc STP	X26, X25, [SP, #80]

0x42bbd0 STP	X24, X23, [SP, #96]

0x42bbd4 STP	X22, X21, [SP, #112]

0x42bbd8 STP	X20, X19, [SP, #128]

0x42bbdc ADD	X29, SP, #48

0x42bbe0 LDR	W25, [X2]

0x42bbe4 LDR	W20, [X3]

0x42bbe8 LDR	W8, [X4]

0x42bbec SUB	W21, W25, W20

0x42bbf0 ADD	W8, W8, W20

0x42bbf4 SUBS	W26, W8, W21

0x42bbf8 B.LT	42bc70

0x42bbfc LDR	W19, [X0]

0x42bc00 LDR	X22, [X5, #48]

0x42bc04 LDR	X23, [X5, #64]

0x42bc08 MOVZ	W8, #1

0x42bc0c ADRP	X0,

0x42bc10 ADD	X0, X0, #3528

0x42bc14 SUB	X3, X29, #16

0x42bc18 SUB	X4, X29, #4

0x42bc1c LDR	W24, [X6]

0x42bc20 SUB	X5, X29, #8

0x42bc24 SUB	X6, X29, #12

0x42bc28 MOVZ	W2, #34

0x42bc2c STP	W26, WZR, [X29, #504]

0x42bc30 STP	WZR, W8, [X29, #496]

0x42bc34 STR	W8, [SP]

0x42bc38 MOVZ	W7, #1

0x42bc3c ORR	W1, WZR, W19

0x42bc40 BL	402f40

0x42bc44 LDP	W8, W9, [X29, #504]

0x42bc48 CMP	W8, W26

0x42bc4c CSEL	W8, W8, W26, #3

0x42bc50 ADD	W10, W8, #1

0x42bc54 CMP	W9, W10

0x42bc58 CCMP	W20, #1, #8, #3

0x42bc5c B.GE	42bc90

(363) 0x42bc60 ORR	W1, WZR, W19

(363) 0x42bc64 ADRP	X0,

(363) 0x42bc68 ADD	X0, X0, #3552

(363) 0x42bc6c BL	402d80

(363) 0x42bc70 LDP	X20, X19, [SP, #128]

(363) 0x42bc74 LDP	X22, X21, [SP, #112]

(363) 0x42bc78 LDP	X24, X23, [SP, #96]

(363) 0x42bc7c LDP	X26, X25, [SP, #80]

(363) 0x42bc80 LDP	X28, X27, [SP, #64]

(363) 0x42bc84 LDP	X29, X30, [SP, #48]

(363) 0x42bc88 ADD	SP, SP, #144

(363) 0x42bc8c RET

(363) 0x42bc90 ADD	W11, W24, #1

(363) 0x42bc94 UBFM	X18, X20, #61, #60

(363) 0x42bc98 ADD	W15, W24, #2

(363) 0x42bc9c SUB	X0, X20, #1

(363) 0x42bca0 ADD	W14, W9, W25

(363) 0x42bca4 ORR	W10, WZR, WZR

(363) 0x42bca8 PTRUE	P0.D, ALL

(363) 0x42bcac UBFM	X13, X22, #61, #60

(363) 0x42bcb0 SBFM	X16, X11, #61, #31

(363) 0x42bcb4 ADD	X1, X23, X18

(363) 0x42bcb8 SBFM	X17, X15, #61, #31

(363) 0x42bcbc ADD	X12, X23, X16

(363) 0x42bcc0 STP	X12, X11, [SP, #16]

(363) 0x42bcc4 ADD	X16, X16, #8

(363) 0x42bcc8 ADD	X15, X23, X17

(363) 0x42bccc ADD	X1, X1, X17

(363) 0x42bcd0 SUB	X17, X16, X18

(363) 0x42bcd4 ADD	X3, X23, X16

(363) 0x42bcd8 CNTW	X16, ALL

(363) 0x42bcdc CMP	X16, #28

(363) 0x42bce0 ADD	X2, X23, X17

(363) 0x42bce4 MOVZ	W17, #28

(363) 0x42bce8 SUB	W18, W11, W0

(363) 0x42bcec CSEL	X17, X16, X17, #8

(363) 0x42bcf0 ANDS	XZR, X0, #6112

(363) 0x42bcf4 SUB	W14, W14, W20

(363) 0x42bcf8 ADD	W12, W14, #1

(363) 0x42bcfc SUB	X0, XZR, X0,LSL #3

(363) 0x42bd00 CCMP	W18, W11, #0, #0

(363) 0x42bd04 ADD	X11, X15, #16

(363) 0x42bd08 ORR	W5, WZR, W12

(363) 0x42bd0c STR	X11, [SP, #8]

(363) 0x42bd10 CNTD	X11, ALL

(363) 0x42bd14 CSINC	W18, WZR, WZR, #13

(363) 0x42bd18 CMP	X15, X3

(363) 0x42bd1c MOVZ	W3, #1

(363) 0x42bd20 CCMP	X2, X1, #2, #3

(363) 0x42bd24 ORR	W2, WZR, W12

(363) 0x42bd28 SUB	X4, X3, X11

(363) 0x42bd2c CSINC	W1, WZR, WZR, #2

(363) 0x42bd30 B	42bd54

0x42bd34 HINT	#0

0x42bd38 HINT	#0

0x42bd3c HINT	#0

(363) 0x42bd40 CMP	W9, W8

(363) 0x42bd44 ORR	W9, WZR, W6

(363) 0x42bd48 ADD	W10, W10, #1

(363) 0x42bd4c ADD	W5, W5, #1

(363) 0x42bd50 B.EQ	42bc60

(363) 0x42bd54 ADD	W6, W9, #1

(363) 0x42bd58 SBFM	X25, X5, #0, #31

(363) 0x42bd5c CMP	X17, X20

(363) 0x42bd60 ADD	W3, W6, W21

(363) 0x42bd64 MADD	X26, X13, X25, X15

(363) 0x42bd68 SBFM	X3, X3, #0, #31

(363) 0x42bd6c MADD	X3, X22, X3, XZR

(363) 0x42bd70 ADD	X7, X23, X3,LSL #3

(363) 0x42bd74 B.LS	42bd80

(363) 0x42bd78 ORR	X27, XZR, XZR

(363) 0x42bd7c B	42be4c

(363) 0x42bd80 LDR	X12, [SP, #16]

(363) 0x42bd84 ADD	W3, W2, W10

(363) 0x42bd88 ORR	W14, WZR, W19

(363) 0x42bd8c SBFM	X3, X3, #0, #31

(363) 0x42bd90 MADD	X3, X13, X3, X12

(363) 0x42bd94 ADD	X19, X3, X0

(363) 0x42bd98 CMP	X19, X3

(363) 0x42bd9c CSINC	W3, W18, WZR, #9

(363) 0x42bda0 ORR	W3, W3, W1

(363) 0x42bda4 TBZ	W3, #0, 42bdc0

0x42bda8 ORR	X27, XZR, XZR

0x42bdac ORR	W19, WZR, W14

0x42bdb0 B	42be4c

0x42bdb4 HINT	#0

0x42bdb8 HINT	#0

0x42bdbc HINT	#0

(363) 0x42bdc0 UDIV	X3, X20, X16

(363) 0x42bdc4 CNTD	X12, ALL

(363) 0x42bdc8 ORR	W11, WZR, W1

(363) 0x42bdcc ORR	X1, XZR, X0

(363) 0x42bdd0 ORR	W0, WZR, W18

(363) 0x42bdd4 ORR	W18, WZR, W2

(363) 0x42bdd8 ORR	W2, WZR, W24

(363) 0x42bddc ORR	X28, XZR, XZR

(363) 0x42bde0 ADDVL	X19, X26, #1

(363) 0x42bde4 UMSUBL	X30, W3, W16, X20

(363) 0x42bde8 UMADDL	X27, W3, W16, XZR

(363) 0x42bdec SUB	X3, XZR, X12

(363) 0x42bdf0 LDR	X12, [SP, #24]

(363) 0x42bdf4 ORR	W24, WZR, W12

(363) 0x42bdf8 HINT	#0

(363) 0x42bdfc HINT	#0

  (362) 0x42be00 ADD	X12, X7, W24,SXTW #3

  (362) 0x42be04 SUB	W24, W24, W16

  (362) 0x42be08 ADD	X12, X12, X4,LSL #3

  (362) 0x42be0c LD1D	{Z0.D}, P0/Z, [X12, MUL VL]

  (362) 0x42be10 LD1D	{Z1.D}, P0/Z, [X12, X3,LSL #3]

  (362) 0x42be14 REV	Z0.D, Z0.D

  (362) 0x42be18 REV	Z1.D, Z1.D

  (362) 0x42be1c ST1D	{Z0.D}, P0, [X26, X28,LSL #3]

  (362) 0x42be20 ST1D	{Z1.D}, P0, [X19, X28,LSL #3]

  (362) 0x42be24 ADD	X28, X28, X16

  (362) 0x42be28 CMP	X27, X28

  (362) 0x42be2c B.NE	42be00

(363) 0x42be30 ORR	W24, WZR, W2

(363) 0x42be34 ORR	W19, WZR, W14

(363) 0x42be38 ORR	W2, WZR, W18

(363) 0x42be3c ORR	W18, WZR, W0

(363) 0x42be40 ORR	X0, XZR, X1

(363) 0x42be44 ORR	W1, WZR, W11

(363) 0x42be48 CBZ	X30, 42bd40

(363) 0x42be4c SUB	W12, W20, W27

(363) 0x42be50 ORR	X28, XZR, X27

(363) 0x42be54 ANDS	X30, X12, #4160

(363) 0x42be58 B.EQ	42be80

(363) 0x42be5c LDR	X12, [SP, #24]

(363) 0x42be60 ORR	X28, XZR, X27

(363) 0x42be64 SUB	W3, W12, W27

  (365) 0x42be68 LDR	D0, [X7, X3,SXTW #3]

  (365) 0x42be6c SUB	W3, W3, #1

  (365) 0x42be70 SUBS	X30, X30, #1

  (365) 0x42be74 STR	D0, [X26, X28,LSL #3]

  (365) 0x42be78 ADD	X28, X28, #1

  (365) 0x42be7c B.NE	42be68

(363) 0x42be80 ORN	X12, XZR, X27

(363) 0x42be84 ADD	X12, X12, X20

(363) 0x42be88 CMP	X12, #3

(363) 0x42be8c B.CC	42bd40

0x42be90 MADD	X12, X13, X25, XZR

0x42be94 LDR	X14, [SP, #8]

0x42be98 SUB	X25, X20, X28

0x42be9c SUB	W26, W24, W28

0x42bea0 ADD	X12, X12, X28,LSL #3

0x42bea4 ADD	X27, X14, X12

(364) 0x42bea8 ADD	W12, W26, #1

(364) 0x42beac SUB	X25, X25, #4

(364) 0x42beb0 LDR	D0, [X7, X12,SXTW #3]

(364) 0x42beb4 SUB	W12, W26, #1

(364) 0x42beb8 STUR	D0, [X27, #496]

(364) 0x42bebc LDR	D0, [X7, X26,SXTW #3]

(364) 0x42bec0 STUR	D0, [X27, #504]

(364) 0x42bec4 LDR	D0, [X7, X12,SXTW #3]

(364) 0x42bec8 SUB	W12, W26, #2

(364) 0x42becc SUB	W26, W26, #4

(364) 0x42bed0 STR	D0, [X27]

(364) 0x42bed4 LDR	D0, [X7, X12,SXTW #3]

(364) 0x42bed8 STR	D0, [X27, #8]

(364) 0x42bedc ADD	X27, X27, #32

(364) 0x42bee0 CBNZ	X25, 42bea8

0x42bee4 B	42bd40

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:160-163
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:160-163

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 7.00 to 0.91 cycles (7.72x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

7% of peak load performance is reached (7.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
34% of peak store performance is reached (16.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42bbc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42bc70 <.omp_outlined..22+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <463c0c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42bc90 <.omp_outlined..22+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42be4c <.omp_outlined..22+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
MADD X12, X13, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42bd40 <.omp_outlined..22+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.cpp:160-163
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:160-163

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

7% of peak load performance is reached (7.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
34% of peak store performance is reached (16.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42bbc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42bc70 <.omp_outlined..22+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <463c0c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3528	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42bc90 <.omp_outlined..22+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42be4c <.omp_outlined..22+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
MADD X12, X13, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42bd40 <.omp_outlined..22+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined..22#0x42bbc0–	0.01	0
▼Loop 363 - update_halo.cpp:160-163 - exec–	0	0
○Loop 365 - update_halo.cpp:162-163 - exec	0.01	0
○Loop 362 - update_halo.cpp:162-163 - exec	0	0
○Loop 364 - update_halo.cpp:162-163 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code