OV - exec - Function .omp_outlined..20#0x42b950

	Function: .omp_outlined..20#0x42b950	Module: exec	Source: update_halo.cpp:150-153	Coverage: 0.01%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 150 - 153

--------------------------------------------------------------------------------

150: #pragma omp parallel for simd

151:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

152:         for (int j = 0; j < depth; ++j) {

153:           field.energy0(1 - j, k) = field.energy0(2 + j, k);

0x42b950 SUB	SP, SP, #128

0x42b954 STP	X29, X30, [SP, #32]

0x42b958 STP	X28, X27, [SP, #48]

0x42b95c STP	X26, X25, [SP, #64]

0x42b960 STP	X24, X23, [SP, #80]

0x42b964 STP	X22, X21, [SP, #96]

0x42b968 STP	X20, X19, [SP, #112]

0x42b96c ADD	X29, SP, #32

0x42b970 LDR	W22, [X2]

0x42b974 LDR	W20, [X3]

0x42b978 LDR	W8, [X4]

0x42b97c SUB	W9, W22, W20

0x42b980 ADD	W8, W8, W20

0x42b984 SUBS	W24, W8, W9

0x42b988 B.LT	42ba00

0x42b98c LDR	W19, [X0]

0x42b990 LDR	X23, [X5, #48]

0x42b994 LDR	X21, [X5, #64]

0x42b998 MOVZ	W8, #1

0x42b99c ADRP	X0,

0x42b9a0 ADD	X0, X0, #3456

0x42b9a4 ADD	X3, SP, #16

0x42b9a8 SUB	X4, X29, #4

0x42b9ac STP	W24, WZR, [X29, #504]

0x42b9b0 SUB	X5, X29, #8

0x42b9b4 SUB	X6, X29, #12

0x42b9b8 MOVZ	W2, #34

0x42b9bc STUR	W8, [X29, #500]

0x42b9c0 STR	WZR, [SP, #16]

0x42b9c4 STR	W8, [SP]

0x42b9c8 MOVZ	W7, #1

0x42b9cc ORR	W1, WZR, W19

0x42b9d0 BL	402f40

0x42b9d4 LDP	W8, W9, [X29, #504]

0x42b9d8 CMP	W8, W24

0x42b9dc CSEL	W8, W8, W24, #3

0x42b9e0 ADD	W10, W8, #1

0x42b9e4 CMP	W9, W10

0x42b9e8 CCMP	W20, #1, #8, #3

0x42b9ec B.GE	42ba20

(350) 0x42b9f0 ORR	W1, WZR, W19

(350) 0x42b9f4 ADRP	X0,

(350) 0x42b9f8 ADD	X0, X0, #3480

(350) 0x42b9fc BL	402d80

(350) 0x42ba00 LDP	X20, X19, [SP, #112]

(350) 0x42ba04 LDP	X22, X21, [SP, #96]

(350) 0x42ba08 LDP	X24, X23, [SP, #80]

(350) 0x42ba0c LDP	X26, X25, [SP, #64]

(350) 0x42ba10 LDP	X28, X27, [SP, #48]

(350) 0x42ba14 LDP	X29, X30, [SP, #32]

(350) 0x42ba18 ADD	SP, SP, #128

(350) 0x42ba1c RET

(350) 0x42ba20 ADD	W15, W9, W22

(350) 0x42ba24 CNTW	X11, ALL

(350) 0x42ba28 SUB	X2, X20, #1

(350) 0x42ba2c ADD	X14, X21, #16

(350) 0x42ba30 MOVZ	W17, #12

(350) 0x42ba34 RDVL	X4, #1

(350) 0x42ba38 ORR	W10, WZR, WZR

(350) 0x42ba3c ADD	X12, X21, #8

(350) 0x42ba40 UBFM	X13, X23, #61, #60

(350) 0x42ba44 RDVL	X18, #2

(350) 0x42ba48 RDVL	X0, #62

(350) 0x42ba4c ADD	X1, X21, #24

(350) 0x42ba50 CMP	X11, #12

(350) 0x42ba54 SUB	W16, W15, W20

(350) 0x42ba58 SUB	X15, XZR, X2,LSL #3

(350) 0x42ba5c UBFM	X2, X2, #61, #63

(350) 0x42ba60 CSEL	X17, X11, X17, #8

(350) 0x42ba64 ADDVL	X3, X14, #1

(350) 0x42ba68 SUB	X4, X14, X4

(350) 0x42ba6c ADD	W16, W16, #1

(350) 0x42ba70 ADDVL	X5, X14, #62

(350) 0x42ba74 PTRUE	P0.B, ALL

(350) 0x42ba78 ORR	W6, WZR, W16

(350) 0x42ba7c B	42ba94

(350) 0x42ba80 CMP	W9, W8

(350) 0x42ba84 ADD	W9, W9, #1

(350) 0x42ba88 ADD	W10, W10, #1

(350) 0x42ba8c ADD	W6, W6, #1

(350) 0x42ba90 B.EQ	42b9f0

(350) 0x42ba94 SBFM	X7, X6, #0, #31

(350) 0x42ba98 CMP	X17, X20

(350) 0x42ba9c MADD	X7, X13, X7, XZR

(350) 0x42baa0 B.HI	42bac0

(350) 0x42baa4 ADD	W22, W16, W10

(350) 0x42baa8 SBFM	X22, X22, #0, #31

(350) 0x42baac MADD	X22, X13, X22, X12

(350) 0x42bab0 ADD	X23, X22, X15

(350) 0x42bab4 CMP	X23, X22

(350) 0x42bab8 CCMP	X2, #0, #0, #9

(350) 0x42babc B.EQ	42bb60

(350) 0x42bac0 ORR	X22, XZR, XZR

(350) 0x42bac4 SUB	W23, W20, W22

(350) 0x42bac8 ANDS	X24, X23, #4160

(350) 0x42bacc ORR	X23, XZR, X22

(350) 0x42bad0 B.EQ	42baf8

(350) 0x42bad4 SUB	X23, X7, X22,LSL #3

(350) 0x42bad8 ADD	X25, X14, X7

(350) 0x42badc ADD	X26, X12, X23

(350) 0x42bae0 ORR	X23, XZR, X22

  (352) 0x42bae4 LDR	D0, [X25, X23,LSL #3]

  (352) 0x42bae8 ADD	X23, X23, #1

  (352) 0x42baec SUBS	X24, X24, #1

  (352) 0x42baf0 STR	D0, [X26], #504

  (352) 0x42baf4 B.NE	42bae4

(350) 0x42baf8 ORN	X22, XZR, X22

(350) 0x42bafc ADD	X22, X22, X20

(350) 0x42bb00 CMP	X22, #3

(350) 0x42bb04 B.CC	42ba80

(350) 0x42bb08 UBFM	X24, X23, #61, #60

(350) 0x42bb0c SUB	X23, X20, X23

(350) 0x42bb10 SUB	X22, X7, X24

(350) 0x42bb14 ADD	X7, X7, X24

(350) 0x42bb18 ADD	X22, X21, X22

(350) 0x42bb1c ADD	X7, X1, X7

  (351) 0x42bb20 LDUR	D0, [X7, #504]

  (351) 0x42bb24 SUBS	X23, X23, #4

  (351) 0x42bb28 STR	D0, [X22, #8]

  (351) 0x42bb2c LDR	D0, [X7]

  (351) 0x42bb30 STR	D0, [X22]

  (351) 0x42bb34 LDR	D0, [X7, #8]

  (351) 0x42bb38 STUR	D0, [X22, #504]

  (351) 0x42bb3c LDR	D0, [X7, #16]

  (351) 0x42bb40 ADD	X7, X7, #32

  (351) 0x42bb44 STUR	D0, [X22, #496]

  (351) 0x42bb48 SUB	X22, X22, #32

  (351) 0x42bb4c B.NE	42bb20

(350) 0x42bb50 B	42ba80

0x42bb54 HINT	#0

0x42bb58 HINT	#0

0x42bb5c HINT	#0

(350) 0x42bb60 UDIV	X22, X20, X11

(350) 0x42bb64 ORR	X25, XZR, X5

(350) 0x42bb68 ORR	X26, XZR, X4

(350) 0x42bb6c ORR	X27, XZR, X3

(350) 0x42bb70 ORR	X28, XZR, X14

(350) 0x42bb74 UMSUBL	X23, W22, W11, X20

(350) 0x42bb78 UMADDL	X22, W22, W11, XZR

(350) 0x42bb7c ORR	X24, XZR, X22

  (353) 0x42bb80 LD1B	{Z0.B}, P0/Z, [X28, X7]

  (353) 0x42bb84 LD1B	{Z1.B}, P0/Z, [X27, X7]

  (353) 0x42bb88 ADD	X28, X28, X18

  (353) 0x42bb8c ADD	X27, X27, X18

  (353) 0x42bb90 SUBS	X24, X24, X11

  (353) 0x42bb94 REV	Z0.D, Z0.D

  (353) 0x42bb98 ST1B	{Z0.B}, P0, [X26, X7]

  (353) 0x42bb9c REV	Z0.D, Z1.D

  (353) 0x42bba0 ADD	X26, X26, X0

  (353) 0x42bba4 ST1B	{Z0.B}, P0, [X25, X7]

  (353) 0x42bba8 ADD	X25, X25, X0

  (353) 0x42bbac B.NE	42bb80

(350) 0x42bbb0 CBNZ	X23, 42bac4

0x42bbb4 B	42ba80

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:150-153
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:150-153.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.67 to 0.71 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	44
loop length	176
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42b950

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42ba00 <.omp_outlined..20+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <46399c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3456	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42ba20 <.omp_outlined..20+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 42ba80 <.omp_outlined..20+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.cpp:150-153
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:150-153.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	44
loop length	176
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42b950

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42ba00 <.omp_outlined..20+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <46399c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3456	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42ba20 <.omp_outlined..20+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 42ba80 <.omp_outlined..20+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined..20#0x42b950–	0.01	0
▼Loop 350 - update_halo.cpp:150-153 - exec–	0	0
○Loop 352 - update_halo.cpp:152-153 - exec	0.01	0
○Loop 351 - update_halo.cpp:152-153 - exec	0	0
○Loop 353 - update_halo.cpp:152-153 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code