OV - exec - Function .omp_outlined..14#0x42b260

	Function: .omp_outlined..14#0x42b260	Module: exec	Source: update_halo.cpp:117-120 [...]	Coverage: 0.02%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 117 - 120

--------------------------------------------------------------------------------

117: #pragma omp parallel for simd

118:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

119:         for (int j = 0; j < depth; ++j) {

120:           field.density1(x_max + 2 + j, k) = field.density1(x_max + 1 - j, k);

0x42b260 SUB	SP, SP, #144

0x42b264 STP	X29, X30, [SP, #48]

0x42b268 STP	X28, X27, [SP, #64]

0x42b26c STP	X26, X25, [SP, #80]

0x42b270 STP	X24, X23, [SP, #96]

0x42b274 STP	X22, X21, [SP, #112]

0x42b278 STP	X20, X19, [SP, #128]

0x42b27c ADD	X29, SP, #48

0x42b280 LDR	W25, [X2]

0x42b284 LDR	W20, [X3]

0x42b288 LDR	W8, [X4]

0x42b28c SUB	W21, W25, W20

0x42b290 ADD	W8, W8, W20

0x42b294 SUBS	W26, W8, W21

0x42b298 B.LT	42b310

0x42b29c LDR	W19, [X0]

0x42b2a0 LDR	X22, [X5, #24]

0x42b2a4 LDR	X23, [X5, #40]

0x42b2a8 MOVZ	W8, #1

0x42b2ac ADRP	X0,

0x42b2b0 ADD	X0, X0, #3240

0x42b2b4 SUB	X3, X29, #16

0x42b2b8 SUB	X4, X29, #4

0x42b2bc LDR	W24, [X6]

0x42b2c0 SUB	X5, X29, #8

0x42b2c4 SUB	X6, X29, #12

0x42b2c8 MOVZ	W2, #34

0x42b2cc STP	W26, WZR, [X29, #504]

0x42b2d0 STP	WZR, W8, [X29, #496]

0x42b2d4 STR	W8, [SP]

0x42b2d8 MOVZ	W7, #1

0x42b2dc ORR	W1, WZR, W19

0x42b2e0 BL	402f40

0x42b2e4 LDP	W8, W9, [X29, #504]

0x42b2e8 CMP	W8, W26

0x42b2ec CSEL	W8, W8, W26, #3

0x42b2f0 ADD	W10, W8, #1

0x42b2f4 CMP	W9, W10

0x42b2f8 CCMP	W20, #1, #8, #3

0x42b2fc B.GE	42b330

(317) 0x42b300 ORR	W1, WZR, W19

(317) 0x42b304 ADRP	X0,

(317) 0x42b308 ADD	X0, X0, #3264

(317) 0x42b30c BL	402d80

(317) 0x42b310 LDP	X20, X19, [SP, #128]

(317) 0x42b314 LDP	X22, X21, [SP, #112]

(317) 0x42b318 LDP	X24, X23, [SP, #96]

(317) 0x42b31c LDP	X26, X25, [SP, #80]

(317) 0x42b320 LDP	X28, X27, [SP, #64]

(317) 0x42b324 LDP	X29, X30, [SP, #48]

(317) 0x42b328 ADD	SP, SP, #144

(317) 0x42b32c RET

(317) 0x42b330 ADD	W11, W24, #1

(317) 0x42b334 UBFM	X18, X20, #61, #60

(317) 0x42b338 ADD	W15, W24, #2

(317) 0x42b33c SUB	X0, X20, #1

(317) 0x42b340 ADD	W14, W9, W25

(317) 0x42b344 ORR	W10, WZR, WZR

(317) 0x42b348 PTRUE	P0.D, ALL

(317) 0x42b34c UBFM	X13, X22, #61, #60

(317) 0x42b350 SBFM	X16, X11, #61, #31

(317) 0x42b354 ADD	X1, X23, X18

(317) 0x42b358 SBFM	X17, X15, #61, #31

(317) 0x42b35c ADD	X12, X23, X16

(317) 0x42b360 STP	X12, X11, [SP, #16]

(317) 0x42b364 ADD	X16, X16, #8

(317) 0x42b368 ADD	X15, X23, X17

(317) 0x42b36c ADD	X1, X1, X17

(317) 0x42b370 SUB	X17, X16, X18

(317) 0x42b374 ADD	X3, X23, X16

(317) 0x42b378 CNTW	X16, ALL

(317) 0x42b37c CMP	X16, #28

(317) 0x42b380 ADD	X2, X23, X17

(317) 0x42b384 MOVZ	W17, #28

(317) 0x42b388 SUB	W18, W11, W0

(317) 0x42b38c CSEL	X17, X16, X17, #8

(317) 0x42b390 ANDS	XZR, X0, #6112

(317) 0x42b394 SUB	W14, W14, W20

(317) 0x42b398 ADD	W12, W14, #1

(317) 0x42b39c SUB	X0, XZR, X0,LSL #3

(317) 0x42b3a0 CCMP	W18, W11, #0, #0

(317) 0x42b3a4 ADD	X11, X15, #16

(317) 0x42b3a8 ORR	W5, WZR, W12

(317) 0x42b3ac STR	X11, [SP, #8]

(317) 0x42b3b0 CNTD	X11, ALL

(317) 0x42b3b4 CSINC	W18, WZR, WZR, #13

(317) 0x42b3b8 CMP	X15, X3

(317) 0x42b3bc MOVZ	W3, #1

(317) 0x42b3c0 CCMP	X2, X1, #2, #3

(317) 0x42b3c4 ORR	W2, WZR, W12

(317) 0x42b3c8 SUB	X4, X3, X11

(317) 0x42b3cc CSINC	W1, WZR, WZR, #2

(317) 0x42b3d0 B	42b3f4

0x42b3d4 HINT	#0

0x42b3d8 HINT	#0

0x42b3dc HINT	#0

(317) 0x42b3e0 CMP	W9, W8

(317) 0x42b3e4 ORR	W9, WZR, W6

(317) 0x42b3e8 ADD	W10, W10, #1

(317) 0x42b3ec ADD	W5, W5, #1

(317) 0x42b3f0 B.EQ	42b300

(317) 0x42b3f4 ADD	W6, W9, #1

(317) 0x42b3f8 SBFM	X25, X5, #0, #31

(317) 0x42b3fc CMP	X17, X20

(317) 0x42b400 ADD	W3, W6, W21

(317) 0x42b404 MADD	X26, X13, X25, X15

(317) 0x42b408 SBFM	X3, X3, #0, #31

(317) 0x42b40c MADD	X3, X22, X3, XZR

(317) 0x42b410 ADD	X7, X23, X3,LSL #3

(317) 0x42b414 B.LS	42b420

(317) 0x42b418 ORR	X27, XZR, XZR

(317) 0x42b41c B	42b4ec

(317) 0x42b420 LDR	X12, [SP, #16]

(317) 0x42b424 ADD	W3, W2, W10

(317) 0x42b428 ORR	W14, WZR, W19

(317) 0x42b42c SBFM	X3, X3, #0, #31

(317) 0x42b430 MADD	X3, X13, X3, X12

(317) 0x42b434 ADD	X19, X3, X0

(317) 0x42b438 CMP	X19, X3

(317) 0x42b43c CSINC	W3, W18, WZR, #9

(317) 0x42b440 ORR	W3, W3, W1

(317) 0x42b444 TBZ	W3, #0, 42b460

0x42b448 ORR	X27, XZR, XZR

0x42b44c ORR	W19, WZR, W14

0x42b450 B	42b4ec

0x42b454 HINT	#0

0x42b458 HINT	#0

0x42b45c HINT	#0

(317) 0x42b460 UDIV	X3, X20, X16

(317) 0x42b464 CNTD	X12, ALL

(317) 0x42b468 ORR	W11, WZR, W1

(317) 0x42b46c ORR	X1, XZR, X0

(317) 0x42b470 ORR	W0, WZR, W18

(317) 0x42b474 ORR	W18, WZR, W2

(317) 0x42b478 ORR	W2, WZR, W24

(317) 0x42b47c ORR	X28, XZR, XZR

(317) 0x42b480 ADDVL	X19, X26, #1

(317) 0x42b484 UMSUBL	X30, W3, W16, X20

(317) 0x42b488 UMADDL	X27, W3, W16, XZR

(317) 0x42b48c SUB	X3, XZR, X12

(317) 0x42b490 LDR	X12, [SP, #24]

(317) 0x42b494 ORR	W24, WZR, W12

(317) 0x42b498 HINT	#0

(317) 0x42b49c HINT	#0

  (316) 0x42b4a0 ADD	X12, X7, W24,SXTW #3

  (316) 0x42b4a4 SUB	W24, W24, W16

  (316) 0x42b4a8 ADD	X12, X12, X4,LSL #3

  (316) 0x42b4ac LD1D	{Z0.D}, P0/Z, [X12, MUL VL]

  (316) 0x42b4b0 LD1D	{Z1.D}, P0/Z, [X12, X3,LSL #3]

  (316) 0x42b4b4 REV	Z0.D, Z0.D

  (316) 0x42b4b8 REV	Z1.D, Z1.D

  (316) 0x42b4bc ST1D	{Z0.D}, P0, [X26, X28,LSL #3]

  (316) 0x42b4c0 ST1D	{Z1.D}, P0, [X19, X28,LSL #3]

  (316) 0x42b4c4 ADD	X28, X28, X16

  (316) 0x42b4c8 CMP	X27, X28

  (316) 0x42b4cc B.NE	42b4a0

(317) 0x42b4d0 ORR	W24, WZR, W2

(317) 0x42b4d4 ORR	W19, WZR, W14

(317) 0x42b4d8 ORR	W2, WZR, W18

(317) 0x42b4dc ORR	W18, WZR, W0

(317) 0x42b4e0 ORR	X0, XZR, X1

(317) 0x42b4e4 ORR	W1, WZR, W11

(317) 0x42b4e8 CBZ	X30, 42b3e0

(317) 0x42b4ec SUB	W12, W20, W27

(317) 0x42b4f0 ORR	X28, XZR, X27

(317) 0x42b4f4 ANDS	X30, X12, #4160

(317) 0x42b4f8 B.EQ	42b520

(317) 0x42b4fc LDR	X12, [SP, #24]

(317) 0x42b500 ORR	X28, XZR, X27

(317) 0x42b504 SUB	W3, W12, W27

  (319) 0x42b508 LDR	D0, [X7, X3,SXTW #3]

  (319) 0x42b50c SUB	W3, W3, #1

  (319) 0x42b510 SUBS	X30, X30, #1

  (319) 0x42b514 STR	D0, [X26, X28,LSL #3]

  (319) 0x42b518 ADD	X28, X28, #1

  (319) 0x42b51c B.NE	42b508

(317) 0x42b520 ORN	X12, XZR, X27

(317) 0x42b524 ADD	X12, X12, X20

(317) 0x42b528 CMP	X12, #3

(317) 0x42b52c B.CC	42b3e0

0x42b530 MADD	X12, X13, X25, XZR

0x42b534 LDR	X14, [SP, #8]

0x42b538 SUB	X25, X20, X28

0x42b53c SUB	W26, W24, W28

0x42b540 ADD	X12, X12, X28,LSL #3

0x42b544 ADD	X27, X14, X12

(318) 0x42b548 ADD	W12, W26, #1

(318) 0x42b54c SUB	X25, X25, #4

(318) 0x42b550 LDR	D0, [X7, X12,SXTW #3]

(318) 0x42b554 SUB	W12, W26, #1

(318) 0x42b558 STUR	D0, [X27, #496]

(318) 0x42b55c LDR	D0, [X7, X26,SXTW #3]

(318) 0x42b560 STUR	D0, [X27, #504]

(318) 0x42b564 LDR	D0, [X7, X12,SXTW #3]

(318) 0x42b568 SUB	W12, W26, #2

(318) 0x42b56c SUB	W26, W26, #4

(318) 0x42b570 STR	D0, [X27]

(318) 0x42b574 LDR	D0, [X7, X12,SXTW #3]

(318) 0x42b578 STR	D0, [X27, #8]

(318) 0x42b57c ADD	X27, X27, #32

(318) 0x42b580 CBNZ	X25, 42b548

0x42b584 B	42b3e0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:117-120
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:117-120

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 7.00 to 0.91 cycles (7.72x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

7% of peak load performance is reached (7.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
34% of peak store performance is reached (16.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42b260

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42b310 <.omp_outlined..14+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4632ac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42b330 <.omp_outlined..14+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42b4ec <.omp_outlined..14+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
MADD X12, X13, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42b3e0 <.omp_outlined..14+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.cpp:117-120
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:117-120

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

7% of peak load performance is reached (7.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
34% of peak store performance is reached (16.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42b260

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42b310 <.omp_outlined..14+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4632ac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3240	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42b330 <.omp_outlined..14+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42b4ec <.omp_outlined..14+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
MADD X12, X13, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42b3e0 <.omp_outlined..14+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined..14#0x42b260–	0.02	0.01
▼Loop 317 - update_halo.cpp:117-120 - exec–	0.01	0
○Loop 319 - update_halo.cpp:119-120 - exec	0.01	0
○Loop 316 - update_halo.cpp:119-120 - exec	0	0
○Loop 318 - update_halo.cpp:119-120 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code