OV - exec - Function .omp_outlined..12#0x42aff0

	Function: .omp_outlined..12#0x42aff0	Module: exec	Source: update_halo.cpp:107-110	Coverage: 0.01%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 107 - 110

--------------------------------------------------------------------------------

107: #pragma omp parallel for simd

108:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

109:         for (int j = 0; j < depth; ++j) {

110:           field.density1(1 - j, k) = field.density1(2 + j, k);

0x42aff0 SUB	SP, SP, #128

0x42aff4 STP	X29, X30, [SP, #32]

0x42aff8 STP	X28, X27, [SP, #48]

0x42affc STP	X26, X25, [SP, #64]

0x42b000 STP	X24, X23, [SP, #80]

0x42b004 STP	X22, X21, [SP, #96]

0x42b008 STP	X20, X19, [SP, #112]

0x42b00c ADD	X29, SP, #32

0x42b010 LDR	W22, [X2]

0x42b014 LDR	W20, [X3]

0x42b018 LDR	W8, [X4]

0x42b01c SUB	W9, W22, W20

0x42b020 ADD	W8, W8, W20

0x42b024 SUBS	W24, W8, W9

0x42b028 B.LT	42b0a0

0x42b02c LDR	W19, [X0]

0x42b030 LDR	X23, [X5, #24]

0x42b034 LDR	X21, [X5, #40]

0x42b038 MOVZ	W8, #1

0x42b03c ADRP	X0,

0x42b040 ADD	X0, X0, #3168

0x42b044 ADD	X3, SP, #16

0x42b048 SUB	X4, X29, #4

0x42b04c STP	W24, WZR, [X29, #504]

0x42b050 SUB	X5, X29, #8

0x42b054 SUB	X6, X29, #12

0x42b058 MOVZ	W2, #34

0x42b05c STUR	W8, [X29, #500]

0x42b060 STR	WZR, [SP, #16]

0x42b064 STR	W8, [SP]

0x42b068 MOVZ	W7, #1

0x42b06c ORR	W1, WZR, W19

0x42b070 BL	402f40

0x42b074 LDP	W8, W9, [X29, #504]

0x42b078 CMP	W8, W24

0x42b07c CSEL	W8, W8, W24, #3

0x42b080 ADD	W10, W8, #1

0x42b084 CMP	W9, W10

0x42b088 CCMP	W20, #1, #8, #3

0x42b08c B.GE	42b0c0

(297) 0x42b090 ORR	W1, WZR, W19

(297) 0x42b094 ADRP	X0,

(297) 0x42b098 ADD	X0, X0, #3192

(297) 0x42b09c BL	402d80

(297) 0x42b0a0 LDP	X20, X19, [SP, #112]

(297) 0x42b0a4 LDP	X22, X21, [SP, #96]

(297) 0x42b0a8 LDP	X24, X23, [SP, #80]

(297) 0x42b0ac LDP	X26, X25, [SP, #64]

(297) 0x42b0b0 LDP	X28, X27, [SP, #48]

(297) 0x42b0b4 LDP	X29, X30, [SP, #32]

(297) 0x42b0b8 ADD	SP, SP, #128

(297) 0x42b0bc RET

(297) 0x42b0c0 ADD	W15, W9, W22

(297) 0x42b0c4 CNTW	X11, ALL

(297) 0x42b0c8 SUB	X2, X20, #1

(297) 0x42b0cc ADD	X14, X21, #16

(297) 0x42b0d0 MOVZ	W17, #12

(297) 0x42b0d4 RDVL	X4, #1

(297) 0x42b0d8 ORR	W10, WZR, WZR

(297) 0x42b0dc ADD	X12, X21, #8

(297) 0x42b0e0 UBFM	X13, X23, #61, #60

(297) 0x42b0e4 RDVL	X18, #2

(297) 0x42b0e8 RDVL	X0, #62

(297) 0x42b0ec ADD	X1, X21, #24

(297) 0x42b0f0 CMP	X11, #12

(297) 0x42b0f4 SUB	W16, W15, W20

(297) 0x42b0f8 SUB	X15, XZR, X2,LSL #3

(297) 0x42b0fc UBFM	X2, X2, #61, #63

(297) 0x42b100 CSEL	X17, X11, X17, #8

(297) 0x42b104 ADDVL	X3, X14, #1

(297) 0x42b108 SUB	X4, X14, X4

(297) 0x42b10c ADD	W16, W16, #1

(297) 0x42b110 ADDVL	X5, X14, #62

(297) 0x42b114 PTRUE	P0.B, ALL

(297) 0x42b118 ORR	W6, WZR, W16

(297) 0x42b11c B	42b134

(297) 0x42b120 CMP	W9, W8

(297) 0x42b124 ADD	W9, W9, #1

(297) 0x42b128 ADD	W10, W10, #1

(297) 0x42b12c ADD	W6, W6, #1

(297) 0x42b130 B.EQ	42b090

(297) 0x42b134 SBFM	X7, X6, #0, #31

(297) 0x42b138 CMP	X17, X20

(297) 0x42b13c MADD	X7, X13, X7, XZR

(297) 0x42b140 B.HI	42b160

(297) 0x42b144 ADD	W22, W16, W10

(297) 0x42b148 SBFM	X22, X22, #0, #31

(297) 0x42b14c MADD	X22, X13, X22, X12

(297) 0x42b150 ADD	X23, X22, X15

(297) 0x42b154 CMP	X23, X22

(297) 0x42b158 CCMP	X2, #0, #0, #9

(297) 0x42b15c B.EQ	42b200

(297) 0x42b160 ORR	X22, XZR, XZR

(297) 0x42b164 SUB	W23, W20, W22

(297) 0x42b168 ANDS	X24, X23, #4160

(297) 0x42b16c ORR	X23, XZR, X22

(297) 0x42b170 B.EQ	42b198

(297) 0x42b174 SUB	X23, X7, X22,LSL #3

(297) 0x42b178 ADD	X25, X14, X7

(297) 0x42b17c ADD	X26, X12, X23

(297) 0x42b180 ORR	X23, XZR, X22

  (299) 0x42b184 LDR	D0, [X25, X23,LSL #3]

  (299) 0x42b188 ADD	X23, X23, #1

  (299) 0x42b18c SUBS	X24, X24, #1

  (299) 0x42b190 STR	D0, [X26], #504

  (299) 0x42b194 B.NE	42b184

(297) 0x42b198 ORN	X22, XZR, X22

(297) 0x42b19c ADD	X22, X22, X20

(297) 0x42b1a0 CMP	X22, #3

(297) 0x42b1a4 B.CC	42b120

(297) 0x42b1a8 UBFM	X24, X23, #61, #60

(297) 0x42b1ac SUB	X23, X20, X23

(297) 0x42b1b0 SUB	X22, X7, X24

(297) 0x42b1b4 ADD	X7, X7, X24

(297) 0x42b1b8 ADD	X22, X21, X22

(297) 0x42b1bc ADD	X7, X1, X7

  (298) 0x42b1c0 LDUR	D0, [X7, #504]

  (298) 0x42b1c4 SUBS	X23, X23, #4

  (298) 0x42b1c8 STR	D0, [X22, #8]

  (298) 0x42b1cc LDR	D0, [X7]

  (298) 0x42b1d0 STR	D0, [X22]

  (298) 0x42b1d4 LDR	D0, [X7, #8]

  (298) 0x42b1d8 STUR	D0, [X22, #504]

  (298) 0x42b1dc LDR	D0, [X7, #16]

  (298) 0x42b1e0 ADD	X7, X7, #32

  (298) 0x42b1e4 STUR	D0, [X22, #496]

  (298) 0x42b1e8 SUB	X22, X22, #32

  (298) 0x42b1ec B.NE	42b1c0

(297) 0x42b1f0 B	42b120

0x42b1f4 HINT	#0

0x42b1f8 HINT	#0

0x42b1fc HINT	#0

(297) 0x42b200 UDIV	X22, X20, X11

(297) 0x42b204 ORR	X25, XZR, X5

(297) 0x42b208 ORR	X26, XZR, X4

(297) 0x42b20c ORR	X27, XZR, X3

(297) 0x42b210 ORR	X28, XZR, X14

(297) 0x42b214 UMSUBL	X23, W22, W11, X20

(297) 0x42b218 UMADDL	X22, W22, W11, XZR

(297) 0x42b21c ORR	X24, XZR, X22

  (300) 0x42b220 LD1B	{Z0.B}, P0/Z, [X28, X7]

  (300) 0x42b224 LD1B	{Z1.B}, P0/Z, [X27, X7]

  (300) 0x42b228 ADD	X28, X28, X18

  (300) 0x42b22c ADD	X27, X27, X18

  (300) 0x42b230 SUBS	X24, X24, X11

  (300) 0x42b234 REV	Z0.D, Z0.D

  (300) 0x42b238 ST1B	{Z0.B}, P0, [X26, X7]

  (300) 0x42b23c REV	Z0.D, Z1.D

  (300) 0x42b240 ADD	X26, X26, X0

  (300) 0x42b244 ST1B	{Z0.B}, P0, [X25, X7]

  (300) 0x42b248 ADD	X25, X25, X0

  (300) 0x42b24c B.NE	42b220

(297) 0x42b250 CBNZ	X23, 42b164

0x42b254 B	42b120

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:107-110
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:107-110.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.67 to 0.71 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	44
loop length	176
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42aff0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42b0a0 <.omp_outlined..12+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <46303c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42b0c0 <.omp_outlined..12+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 42b120 <.omp_outlined..12+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.cpp:107-110
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:107-110.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	44
loop length	176
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42aff0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42b0a0 <.omp_outlined..12+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <46303c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3168	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42b0c0 <.omp_outlined..12+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 42b120 <.omp_outlined..12+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined..12#0x42aff0–	0.01	0
▼Loop 297 - update_halo.cpp:107-110 - exec–	0	0
○Loop 299 - update_halo.cpp:109-110 - exec	0.01	0
○Loop 298 - update_halo.cpp:109-110 - exec	0	0
○Loop 300 - update_halo.cpp:109-110 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code