OV - exec - Function .omp_outlined..6#0x42a900

	Function: .omp_outlined..6#0x42a900	Module: exec	Source: update_halo.cpp:74-77 [...]	Coverage: 0.01%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 74 - 77

--------------------------------------------------------------------------------

74: #pragma omp parallel for simd

75:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

76:         for (int j = 0; j < depth; ++j) {

77:           field.density0(x_max + 2 + j, k) = field.density0(x_max + 1 - j, k);

0x42a900 SUB	SP, SP, #144

0x42a904 STP	X29, X30, [SP, #48]

0x42a908 STP	X28, X27, [SP, #64]

0x42a90c STP	X26, X25, [SP, #80]

0x42a910 STP	X24, X23, [SP, #96]

0x42a914 STP	X22, X21, [SP, #112]

0x42a918 STP	X20, X19, [SP, #128]

0x42a91c ADD	X29, SP, #48

0x42a920 LDR	W25, [X2]

0x42a924 LDR	W20, [X3]

0x42a928 LDR	W8, [X4]

0x42a92c SUB	W21, W25, W20

0x42a930 ADD	W8, W8, W20

0x42a934 SUBS	W26, W8, W21

0x42a938 B.LT	42a9b0

0x42a93c LDR	W19, [X0]

0x42a940 LDR	X22, [X5]

0x42a944 LDR	X23, [X5, #16]

0x42a948 MOVZ	W8, #1

0x42a94c ADRP	X0,

0x42a950 ADD	X0, X0, #2952

0x42a954 SUB	X3, X29, #16

0x42a958 SUB	X4, X29, #4

0x42a95c LDR	W24, [X6]

0x42a960 SUB	X5, X29, #8

0x42a964 SUB	X6, X29, #12

0x42a968 MOVZ	W2, #34

0x42a96c STP	W26, WZR, [X29, #504]

0x42a970 STP	WZR, W8, [X29, #496]

0x42a974 STR	W8, [SP]

0x42a978 MOVZ	W7, #1

0x42a97c ORR	W1, WZR, W19

0x42a980 BL	402f40

0x42a984 LDP	W8, W9, [X29, #504]

0x42a988 CMP	W8, W26

0x42a98c CSEL	W8, W8, W26, #3

0x42a990 ADD	W10, W8, #1

0x42a994 CMP	W9, W10

0x42a998 CCMP	W20, #1, #8, #3

0x42a99c B.GE	42a9d0

(246) 0x42a9a0 ORR	W1, WZR, W19

(246) 0x42a9a4 ADRP	X0,

(246) 0x42a9a8 ADD	X0, X0, #2976

(246) 0x42a9ac BL	402d80

(246) 0x42a9b0 LDP	X20, X19, [SP, #128]

(246) 0x42a9b4 LDP	X22, X21, [SP, #112]

(246) 0x42a9b8 LDP	X24, X23, [SP, #96]

(246) 0x42a9bc LDP	X26, X25, [SP, #80]

(246) 0x42a9c0 LDP	X28, X27, [SP, #64]

(246) 0x42a9c4 LDP	X29, X30, [SP, #48]

(246) 0x42a9c8 ADD	SP, SP, #144

(246) 0x42a9cc RET

(246) 0x42a9d0 ADD	W11, W24, #1

(246) 0x42a9d4 UBFM	X18, X20, #61, #60

(246) 0x42a9d8 ADD	W15, W24, #2

(246) 0x42a9dc SUB	X0, X20, #1

(246) 0x42a9e0 ADD	W14, W9, W25

(246) 0x42a9e4 ORR	W10, WZR, WZR

(246) 0x42a9e8 PTRUE	P0.D, ALL

(246) 0x42a9ec UBFM	X13, X22, #61, #60

(246) 0x42a9f0 SBFM	X16, X11, #61, #31

(246) 0x42a9f4 ADD	X1, X23, X18

(246) 0x42a9f8 SBFM	X17, X15, #61, #31

(246) 0x42a9fc ADD	X12, X23, X16

(246) 0x42aa00 STP	X12, X11, [SP, #16]

(246) 0x42aa04 ADD	X16, X16, #8

(246) 0x42aa08 ADD	X15, X23, X17

(246) 0x42aa0c ADD	X1, X1, X17

(246) 0x42aa10 SUB	X17, X16, X18

(246) 0x42aa14 ADD	X3, X23, X16

(246) 0x42aa18 CNTW	X16, ALL

(246) 0x42aa1c CMP	X16, #28

(246) 0x42aa20 ADD	X2, X23, X17

(246) 0x42aa24 MOVZ	W17, #28

(246) 0x42aa28 SUB	W18, W11, W0

(246) 0x42aa2c CSEL	X17, X16, X17, #8

(246) 0x42aa30 ANDS	XZR, X0, #6112

(246) 0x42aa34 SUB	W14, W14, W20

(246) 0x42aa38 ADD	W12, W14, #1

(246) 0x42aa3c SUB	X0, XZR, X0,LSL #3

(246) 0x42aa40 CCMP	W18, W11, #0, #0

(246) 0x42aa44 ADD	X11, X15, #16

(246) 0x42aa48 ORR	W5, WZR, W12

(246) 0x42aa4c STR	X11, [SP, #8]

(246) 0x42aa50 CNTD	X11, ALL

(246) 0x42aa54 CSINC	W18, WZR, WZR, #13

(246) 0x42aa58 CMP	X15, X3

(246) 0x42aa5c MOVZ	W3, #1

(246) 0x42aa60 CCMP	X2, X1, #2, #3

(246) 0x42aa64 ORR	W2, WZR, W12

(246) 0x42aa68 SUB	X4, X3, X11

(246) 0x42aa6c CSINC	W1, WZR, WZR, #2

(246) 0x42aa70 B	42aa94

0x42aa74 HINT	#0

0x42aa78 HINT	#0

0x42aa7c HINT	#0

(246) 0x42aa80 CMP	W9, W8

(246) 0x42aa84 ORR	W9, WZR, W6

(246) 0x42aa88 ADD	W10, W10, #1

(246) 0x42aa8c ADD	W5, W5, #1

(246) 0x42aa90 B.EQ	42a9a0

(246) 0x42aa94 ADD	W6, W9, #1

(246) 0x42aa98 SBFM	X25, X5, #0, #31

(246) 0x42aa9c CMP	X17, X20

(246) 0x42aaa0 ADD	W3, W6, W21

(246) 0x42aaa4 MADD	X26, X13, X25, X15

(246) 0x42aaa8 SBFM	X3, X3, #0, #31

(246) 0x42aaac MADD	X3, X22, X3, XZR

(246) 0x42aab0 ADD	X7, X23, X3,LSL #3

(246) 0x42aab4 B.LS	42aac0

(246) 0x42aab8 ORR	X27, XZR, XZR

(246) 0x42aabc B	42ab8c

(246) 0x42aac0 LDR	X12, [SP, #16]

(246) 0x42aac4 ADD	W3, W2, W10

(246) 0x42aac8 ORR	W14, WZR, W19

(246) 0x42aacc SBFM	X3, X3, #0, #31

(246) 0x42aad0 MADD	X3, X13, X3, X12

(246) 0x42aad4 ADD	X19, X3, X0

(246) 0x42aad8 CMP	X19, X3

(246) 0x42aadc CSINC	W3, W18, WZR, #9

(246) 0x42aae0 ORR	W3, W3, W1

(246) 0x42aae4 TBZ	W3, #0, 42ab00

0x42aae8 ORR	X27, XZR, XZR

0x42aaec ORR	W19, WZR, W14

0x42aaf0 B	42ab8c

0x42aaf4 HINT	#0

0x42aaf8 HINT	#0

0x42aafc HINT	#0

(246) 0x42ab00 UDIV	X3, X20, X16

(246) 0x42ab04 CNTD	X12, ALL

(246) 0x42ab08 ORR	W11, WZR, W1

(246) 0x42ab0c ORR	X1, XZR, X0

(246) 0x42ab10 ORR	W0, WZR, W18

(246) 0x42ab14 ORR	W18, WZR, W2

(246) 0x42ab18 ORR	W2, WZR, W24

(246) 0x42ab1c ORR	X28, XZR, XZR

(246) 0x42ab20 ADDVL	X19, X26, #1

(246) 0x42ab24 UMSUBL	X30, W3, W16, X20

(246) 0x42ab28 UMADDL	X27, W3, W16, XZR

(246) 0x42ab2c SUB	X3, XZR, X12

(246) 0x42ab30 LDR	X12, [SP, #24]

(246) 0x42ab34 ORR	W24, WZR, W12

(246) 0x42ab38 HINT	#0

(246) 0x42ab3c HINT	#0

  (245) 0x42ab40 ADD	X12, X7, W24,SXTW #3

  (245) 0x42ab44 SUB	W24, W24, W16

  (245) 0x42ab48 ADD	X12, X12, X4,LSL #3

  (245) 0x42ab4c LD1D	{Z0.D}, P0/Z, [X12, MUL VL]

  (245) 0x42ab50 LD1D	{Z1.D}, P0/Z, [X12, X3,LSL #3]

  (245) 0x42ab54 REV	Z0.D, Z0.D

  (245) 0x42ab58 REV	Z1.D, Z1.D

  (245) 0x42ab5c ST1D	{Z0.D}, P0, [X26, X28,LSL #3]

  (245) 0x42ab60 ST1D	{Z1.D}, P0, [X19, X28,LSL #3]

  (245) 0x42ab64 ADD	X28, X28, X16

  (245) 0x42ab68 CMP	X27, X28

  (245) 0x42ab6c B.NE	42ab40

(246) 0x42ab70 ORR	W24, WZR, W2

(246) 0x42ab74 ORR	W19, WZR, W14

(246) 0x42ab78 ORR	W2, WZR, W18

(246) 0x42ab7c ORR	W18, WZR, W0

(246) 0x42ab80 ORR	X0, XZR, X1

(246) 0x42ab84 ORR	W1, WZR, W11

(246) 0x42ab88 CBZ	X30, 42aa80

(246) 0x42ab8c SUB	W12, W20, W27

(246) 0x42ab90 ORR	X28, XZR, X27

(246) 0x42ab94 ANDS	X30, X12, #4160

(246) 0x42ab98 B.EQ	42abc0

(246) 0x42ab9c LDR	X12, [SP, #24]

(246) 0x42aba0 ORR	X28, XZR, X27

(246) 0x42aba4 SUB	W3, W12, W27

  (248) 0x42aba8 LDR	D0, [X7, X3,SXTW #3]

  (248) 0x42abac SUB	W3, W3, #1

  (248) 0x42abb0 SUBS	X30, X30, #1

  (248) 0x42abb4 STR	D0, [X26, X28,LSL #3]

  (248) 0x42abb8 ADD	X28, X28, #1

  (248) 0x42abbc B.NE	42aba8

(246) 0x42abc0 ORN	X12, XZR, X27

(246) 0x42abc4 ADD	X12, X12, X20

(246) 0x42abc8 CMP	X12, #3

(246) 0x42abcc B.CC	42aa80

0x42abd0 MADD	X12, X13, X25, XZR

0x42abd4 LDR	X14, [SP, #8]

0x42abd8 SUB	X25, X20, X28

0x42abdc SUB	W26, W24, W28

0x42abe0 ADD	X12, X12, X28,LSL #3

0x42abe4 ADD	X27, X14, X12

(247) 0x42abe8 ADD	W12, W26, #1

(247) 0x42abec SUB	X25, X25, #4

(247) 0x42abf0 LDR	D0, [X7, X12,SXTW #3]

(247) 0x42abf4 SUB	W12, W26, #1

(247) 0x42abf8 STUR	D0, [X27, #496]

(247) 0x42abfc LDR	D0, [X7, X26,SXTW #3]

(247) 0x42ac00 STUR	D0, [X27, #504]

(247) 0x42ac04 LDR	D0, [X7, X12,SXTW #3]

(247) 0x42ac08 SUB	W12, W26, #2

(247) 0x42ac0c SUB	W26, W26, #4

(247) 0x42ac10 STR	D0, [X27]

(247) 0x42ac14 LDR	D0, [X7, X12,SXTW #3]

(247) 0x42ac18 STR	D0, [X27, #8]

(247) 0x42ac1c ADD	X27, X27, #32

(247) 0x42ac20 CBNZ	X25, 42abe8

0x42ac24 B	42aa80

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:74-77
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:74-77

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 7.00 to 0.91 cycles (7.72x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

7% of peak load performance is reached (7.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
34% of peak store performance is reached (16.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42a900

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42a9b0 <.omp_outlined..6+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <46394c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2952	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42a9d0 <.omp_outlined..6+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42ab8c <.omp_outlined..6+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
MADD X12, X13, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42aa80 <.omp_outlined..6+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.cpp:74-77
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:74-77

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

7% of peak load performance is reached (7.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
34% of peak store performance is reached (16.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42a900

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42a9b0 <.omp_outlined..6+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <46394c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2952	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42a9d0 <.omp_outlined..6+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42ab8c <.omp_outlined..6+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
MADD X12, X13, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42aa80 <.omp_outlined..6+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined..6#0x42a900–	0.01	0
▼Loop 246 - update_halo.cpp:74-77 - exec–	0	0
○Loop 248 - update_halo.cpp:76-77 - exec	0.01	0
○Loop 245 - update_halo.cpp:76-77 - exec	0	0
○Loop 247 - update_halo.cpp:76-77 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code