OV - exec - Function .omp_outlined..2#0x427e20

	Function: .omp_outlined..2#0x427e20	Module: exec	Source: PdV.cpp:69-83 [...]	Coverage: 7.87%

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp: 69 - 83

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69: #pragma omp parallel for simd collapse(2)

70:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

71:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x427e20 STP	D15, D14, [SP, #864]!

0x427e24 STP	D13, D12, [SP, #16]

0x427e28 STP	D11, D10, [SP, #32]

0x427e2c STP	D9, D8, [SP, #48]

0x427e30 STP	X29, X30, [SP, #64]

0x427e34 STP	X28, X27, [SP, #80]

0x427e38 STP	X26, X25, [SP, #96]

0x427e3c STP	X24, X23, [SP, #112]

0x427e40 STP	X22, X21, [SP, #128]

0x427e44 STP	X20, X19, [SP, #144]

0x427e48 ADD	X29, SP, #64

0x427e4c ADDVL	SP, SP, #61

0x427e50 SUB	SP, SP, #272

0x427e54 LDR	W22, [X2]

0x427e58 LDR	W8, [X3]

0x427e5c ADD	W10, W22, #1

0x427e60 ADD	W8, W8, #2

0x427e64 SUBS	W8, W8, W10

0x427e68 B.LE	428554

0x427e6c LDR	W21, [X4]

0x427e70 LDR	W9, [X5]

0x427e74 ADD	W3, W21, #1

0x427e78 ADD	W9, W9, #2

0x427e7c CMP	W9, W3

0x427e80 B.LE	428554

0x427e84 LDP	X17, X16, [X29, #128]

0x427e88 LDP	X1, X18, [X29, #112]

0x427e8c LDR	X2, [X29, #96]

0x427e90 LDP	X15, X14, [X29, #144]

0x427e94 LDR	X5, [X6]

0x427e98 LDP	X13, X12, [X29, #160]

0x427e9c STR	X10, [SP, #216]

0x427ea0 LDP	X11, X10, [X29, #176]

0x427ea4 LDR	X23, [X6, #16]

0x427ea8 LDR	X6, [X7]

0x427eac LDR	X25, [X7, #16]

0x427eb0 MOVZ	W7, #1

0x427eb4 STR	WZR, [SP, #244]

0x427eb8 LDR	X4, [X2]

0x427ebc LDR	X27, [X2, #16]

0x427ec0 LDR	X2, [X1]

0x427ec4 LDR	X19, [X1, #16]

0x427ec8 LDR	X1, [X18]

0x427ecc LDR	X20, [X18, #16]

0x427ed0 LDR	X18, [X17]

0x427ed4 LDR	X24, [X17, #16]

0x427ed8 LDR	X17, [X16]

0x427edc LDR	X26, [X14, #16]

0x427ee0 STP	X17, X5, [SP, #200]

0x427ee4 LDR	X17, [X16, #16]

0x427ee8 LDR	X16, [X15]

0x427eec LDR	X15, [X15, #16]

0x427ef0 STP	X1, X2, [SP, #24]

0x427ef4 ADD	X5, SP, #256

0x427ef8 MOVZ	W2, #34

0x427efc LDR	W1, [X0]

0x427f00 ADRP	X0,

0x427f04 ADD	X0, X0, #2448

0x427f08 STP	X4, X6, [SP, #56]

0x427f0c ADD	X4, SP, #264

0x427f10 ADD	X6, SP, #248

0x427f14 STR	X18, [SP, #48]

0x427f18 STR	X15, [SP, #176]

0x427f1c LDR	X15, [X14]

0x427f20 LDR	X14, [X13]

0x427f24 STP	X16, X17, [SP, #184]

0x427f28 STR	W1, [SP, #76]

0x427f2c STP	X14, X15, [SP, #160]

0x427f30 LDR	X14, [X13, #16]

0x427f34 LDR	X13, [X12]

0x427f38 STP	X13, X14, [SP, #144]

0x427f3c LDR	X13, [X12, #16]

0x427f40 LDR	X12, [X11]

0x427f44 LDR	X11, [X11, #16]

0x427f48 STR	X11, [SP, #120]

0x427f4c SUB	W11, W9, W3

0x427f50 MOVN	X9, #0

0x427f54 UMADDL	X28, W11, W8, X9

0x427f58 LDR	X9, [X10]

0x427f5c STP	X11, X3, [SP, #224]

0x427f60 MOVZ	W8, #1

0x427f64 ADD	X3, SP, #244

0x427f68 STP	X12, X13, [SP, #128]

0x427f6c STR	X8, [SP, #248]

0x427f70 STP	X28, XZR, [SP, #256]

0x427f74 STR	X9, [SP, #112]

0x427f78 LDR	X9, [X10, #16]

0x427f7c STR	X8, [SP]

0x427f80 STR	X9, [SP, #40]

0x427f84 BL	402ee0

0x427f88 LDP	X8, X14, [SP, #256]

0x427f8c CMP	X8, X28

0x427f90 CSEL	X9, X8, X28, #11

0x427f94 CMP	X14, X9

0x427f98 B.GT	428544

0x427f9c LDR	X6, [X29, #104]

0x427fa0 ADD	X0, X9, #1

0x427fa4 CNTD	X11, ALL

0x427fa8 ORR	X10, XZR, X14

0x427fac SUB	X12, X0, X14

0x427fb0 CMP	X12, X11

0x427fb4 B.CC	4282c0

0x427fb8 DUP	Z1.D, X11

0x427fbc SUB	X8, X29, #64

0x427fc0 PTRUE	P0.D, ALL

0x427fc4 FDUP	Z27.D, #80

0x427fc8 STR	Z1, [X8, #511, MUL VL]

0x427fcc UDIV	X10, X12, X11

0x427fd0 LDP	X9, X8, [SP, #216]

0x427fd4 MADD	X13, X10, X11, XZR

0x427fd8 ADD	X10, X14, X13

0x427fdc SUB	X12, X12, X13

0x427fe0 INDEX	Z0.D, X14, #1

0x427fe4 ADD	W14, W22, #2

0x427fe8 DUP	Z1.D, X9

0x427fec DUP	Z2.D, X8

0x427ff0 SUB	X8, X29, #64

0x427ff4 STR	Z1, [X8, #510, MUL VL]

0x427ff8 LDR	X9, [SP, #232]

0x427ffc SUB	X8, X29, #64

0x428000 DUP	Z1.D, X9

0x428004 STR	Z1, [X8, #509, MUL VL]

0x428008 LDR	X8, [SP, #64]

0x42800c LDR	X9, [SP, #208]

0x428010 DUP	Z26.D, X14

0x428014 ADD	W14, W21, #2

0x428018 DUP	Z6.D, X8

0x42801c LDR	X8, [SP, #56]

0x428020 DUP	Z5.D, X9

0x428024 DUP	Z29.D, X14

0x428028 DUP	Z7.D, X8

0x42802c LDP	X8, X17, [SP, #32]

0x428030 DUP	Z16.D, X8

0x428034 LDR	X8, [SP, #24]

0x428038 DUP	Z17.D, X8

0x42803c LDR	X8, [SP, #48]

0x428040 DUP	Z18.D, X8

0x428044 LDR	X8, [SP, #200]

0x428048 DUP	Z19.D, X8

0x42804c LDP	X9, X8, [SP, #176]

0x428050 DUP	Z20.D, X8

0x428054 LDR	X8, [SP, #168]

0x428058 DUP	Z21.D, X8

0x42805c LDP	X14, X8, [SP, #152]

0x428060 DUP	Z22.D, X8

0x428064 LDP	X8, X15, [SP, #128]

0x428068 DUP	Z23.D, X8

0x42806c LDR	X8, [SP, #144]

0x428070 DUP	Z24.D, X8

0x428074 LDP	X8, X16, [SP, #112]

0x428078 DUP	Z25.D, X8

0x42807c LDR	X8, [SP, #192]

(200) 0x428080 SUB	X18, X29, #64

(200) 0x428084 MOVPRFX	Z31, Z0

(200) 0x428088 SDIV	Z31.D, P0/M, Z31.D, Z2.D

(200) 0x42808c MOVPRFX	Z9, Z0

(200) 0x428090 MLS	Z9.D, P0/M, Z31.D, Z2.D

(200) 0x428094 SUBS	X13, X13, X11

(200) 0x428098 LDR	Z1, [X18, #510, MUL VL]

(200) 0x42809c SUB	X18, X29, #64

(200) 0x4280a0 ADD	Z30.D, Z1.D, Z31.D

(200) 0x4280a4 LDR	Z1, [X18, #509, MUL VL]

(200) 0x4280a8 ADD	Z31.D, Z26.D, Z31.D

(200) 0x4280ac MOVPRFX	Z14, Z31

(200) 0x4280b0 SXTW	Z14.D, P0/M, Z31.D

(200) 0x4280b4 MOVPRFX	Z31, Z6

(200) 0x4280b8 MUL	Z31.D, P0/M, Z31.D, Z14.D

(200) 0x4280bc SUB	X18, X29, #64

(200) 0x4280c0 SXTW	Z30.D, P0/M, Z30.D

(200) 0x4280c4 MOVPRFX	Z10, Z5

(200) 0x4280c8 MUL	Z10.D, P0/M, Z10.D, Z30.D

(200) 0x4280cc MOVPRFX	Z12, Z6

(200) 0x4280d0 MUL	Z12.D, P0/M, Z12.D, Z30.D

(200) 0x4280d4 ADD	Z8.D, Z1.D, Z9.D

(200) 0x4280d8 MOVPRFX	Z1, Z7

(200) 0x4280dc MUL	Z1.D, P0/M, Z1.D, Z14.D

(200) 0x4280e0 ADD	Z9.D, Z29.D, Z9.D

(200) 0x4280e4 ADR	Z11.D, [Z10, Z8.D,SXTW]

(200) 0x4280e8 ADR	Z13.D, [Z12, Z8.D,SXTW]

(200) 0x4280ec ADR	Z15.D, [Z31, Z8.D,SXTW]

(200) 0x4280f0 ADR	Z3.D, [Z1, Z8.D,SXTW]

(200) 0x4280f4 ADR	Z10.D, [Z10, Z9.D,SXTW]

(200) 0x4280f8 ADR	Z12.D, [Z12, Z9.D,SXTW]

(200) 0x4280fc ADR	Z31.D, [Z31, Z9.D,SXTW]

(200) 0x428100 ADR	Z1.D, [Z1, Z9.D,SXTW]

(200) 0x428104 LD1D	{Z11.D}, P0/Z, [X23, Z11.D,LSL #3]

(200) 0x428108 LD1D	{Z13.D}, P0/Z, [X25, Z13.D,LSL #3]

(200) 0x42810c LD1D	{Z15.D}, P0/Z, [X25, Z15.D,LSL #3]

(200) 0x428110 FADD	Z13.D, Z13.D, Z15.D

(200) 0x428114 MOVPRFX	Z15, Z7

(200) 0x428118 MUL	Z15.D, P0/M, Z15.D, Z30.D

(200) 0x42811c ADR	Z28.D, [Z15, Z8.D,SXTW]

(200) 0x428120 LD1D	{Z28.D}, P0/Z, [X27, Z28.D,LSL #3]

(200) 0x428124 LD1D	{Z3.D}, P0/Z, [X27, Z3.D,LSL #3]

(200) 0x428128 LD1RD	{Z4.D}, P0/Z, [X6]

(200) 0x42812c LD1D	{Z10.D}, P0/Z, [X23, Z10.D,LSL #3]

(200) 0x428130 LD1D	{Z12.D}, P0/Z, [X25, Z12.D,LSL #3]

(200) 0x428134 LD1D	{Z31.D}, P0/Z, [X25, Z31.D,LSL #3]

(200) 0x428138 FADD	Z28.D, Z13.D, Z28.D

(200) 0x42813c ADR	Z13.D, [Z15, Z9.D,SXTW]

(200) 0x428140 FADD	Z12.D, Z12.D, Z31.D

(200) 0x428144 MOVPRFX	Z31, Z8

(200) 0x428148 SXTW	Z31.D, P0/M, Z8.D

(200) 0x42814c FADD	Z3.D, Z28.D, Z3.D

(200) 0x428150 LD1D	{Z28.D}, P0/Z, [X27, Z13.D,LSL #3]

(200) 0x428154 LD1D	{Z1.D}, P0/Z, [X27, Z1.D,LSL #3]

(200) 0x428158 FMUL	Z3.D, Z11.D, Z3.D

(200) 0x42815c FADD	Z28.D, Z12.D, Z28.D

(200) 0x428160 MOVPRFX	Z12, Z17

(200) 0x428164 MUL	Z12.D, P0/M, Z12.D, Z30.D

(200) 0x428168 ADR	Z13.D, [Z12, Z8.D,SXTW]

(200) 0x42816c ADR	Z12.D, [Z12, Z9.D,SXTW]

(200) 0x428170 FMUL	Z3.D, Z3.D, Z27.D

(200) 0x428174 FADD	Z1.D, Z28.D, Z1.D

(200) 0x428178 MOVPRFX	Z28, Z31

(200) 0x42817c MLA	Z28.D, P0/M, Z16.D, Z30.D

(200) 0x428180 LD1D	{Z28.D}, P0/Z, [X19, Z28.D,LSL #3]

(200) 0x428184 LD1D	{Z11.D}, P0/Z, [X20, Z13.D,LSL #3]

(200) 0x428188 LD1D	{Z12.D}, P0/Z, [X20, Z12.D,LSL #3]

(200) 0x42818c FMUL	Z1.D, Z10.D, Z1.D

(200) 0x428190 FMUL	Z3.D, Z4.D, Z3.D

(200) 0x428194 FADD	Z11.D, Z11.D, Z12.D

(200) 0x428198 MOVPRFX	Z12, Z18

(200) 0x42819c MUL	Z12.D, P0/M, Z12.D, Z30.D

(200) 0x4281a0 ADR	Z13.D, [Z12, Z8.D,SXTW]

(200) 0x4281a4 ADR	Z12.D, [Z12, Z9.D,SXTW]

(200) 0x4281a8 FMUL	Z1.D, Z1.D, Z27.D

(200) 0x4281ac LD1D	{Z13.D}, P0/Z, [X24, Z13.D,LSL #3]

(200) 0x4281b0 LD1D	{Z10.D}, P0/Z, [X24, Z12.D,LSL #3]

(200) 0x4281b4 MOVPRFX	Z12, Z17

(200) 0x4281b8 MUL	Z12.D, P0/M, Z12.D, Z14.D

(200) 0x4281bc FMUL	Z1.D, Z4.D, Z1.D

(200) 0x4281c0 FADD	Z11.D, Z11.D, Z13.D

(200) 0x4281c4 ADR	Z13.D, [Z12, Z8.D,SXTW]

(200) 0x4281c8 ADR	Z12.D, [Z12, Z9.D,SXTW]

(200) 0x4281cc FSUB	Z1.D, Z1.D, Z3.D

(200) 0x4281d0 MOVPRFX	Z3, Z31

(200) 0x4281d4 MLA	Z3.D, P0/M, Z19.D, Z30.D

(200) 0x4281d8 FADD	Z10.D, Z11.D, Z10.D

(200) 0x4281dc MOVPRFX	Z11, Z31

(200) 0x4281e0 MLA	Z11.D, P0/M, Z16.D, Z14.D

(200) 0x4281e4 LD1D	{Z11.D}, P0/Z, [X19, Z11.D,LSL #3]

(200) 0x4281e8 LD1D	{Z13.D}, P0/Z, [X20, Z13.D,LSL #3]

(200) 0x4281ec LD1D	{Z12.D}, P0/Z, [X20, Z12.D,LSL #3]

(200) 0x4281f0 FMUL	Z28.D, Z28.D, Z10.D

(200) 0x4281f4 FADD	Z10.D, Z13.D, Z12.D

(200) 0x4281f8 MOVPRFX	Z12, Z18

(200) 0x4281fc MUL	Z12.D, P0/M, Z12.D, Z14.D

(200) 0x428200 ADR	Z8.D, [Z12, Z8.D,SXTW]

(200) 0x428204 ADR	Z9.D, [Z12, Z9.D,SXTW]

(200) 0x428208 FMUL	Z28.D, Z28.D, Z27.D

(200) 0x42820c LD1D	{Z8.D}, P0/Z, [X24, Z8.D,LSL #3]

(200) 0x428210 LD1D	{Z9.D}, P0/Z, [X24, Z9.D,LSL #3]

(200) 0x428214 LD1D	{Z3.D}, P0/Z, [X8, Z3.D,LSL #3]

(200) 0x428218 FMUL	Z28.D, Z4.D, Z28.D

(200) 0x42821c FADD	Z8.D, Z10.D, Z8.D

(200) 0x428220 MOVPRFX	Z10, Z31

(200) 0x428224 MLA	Z10.D, P0/M, Z22.D, Z30.D

(200) 0x428228 FADD	Z8.D, Z8.D, Z9.D

(200) 0x42822c FMUL	Z8.D, Z11.D, Z8.D

(200) 0x428230 FMUL	Z8.D, Z8.D, Z27.D

(200) 0x428234 FMUL	Z4.D, Z4.D, Z8.D

(200) 0x428238 MOVPRFX	Z8, Z31

(200) 0x42823c MLA	Z8.D, P0/M, Z21.D, Z30.D

(200) 0x428240 FADD	Z1.D, Z1.D, Z4.D

(200) 0x428244 MOVPRFX	Z4, Z31

(200) 0x428248 MLA	Z4.D, P0/M, Z20.D, Z30.D

(200) 0x42824c LD1D	{Z4.D}, P0/Z, [X9, Z4.D,LSL #3]

(200) 0x428250 LD1D	{Z9.D}, P0/Z, [X26, Z8.D,LSL #3]

(200) 0x428254 LD1D	{Z10.D}, P0/Z, [X14, Z10.D,LSL #3]

(200) 0x428258 FSUB	Z1.D, Z1.D, Z28.D

(200) 0x42825c FDUP	Z28.D, #112

(200) 0x428260 FDIV	Z4.D, P0/M, Z4.D, Z9.D

(200) 0x428264 FDIVR	Z9.D, P0/M, Z9.D, Z10.D

(200) 0x428268 FDIV	Z28.D, P0/M, Z28.D, Z3.D

(200) 0x42826c FADD	Z4.D, Z4.D, Z9.D

(200) 0x428270 FMUL	Z4.D, Z4.D, Z1.D

(200) 0x428274 FADD	Z1.D, Z3.D, Z1.D

(200) 0x428278 FDIVR	Z1.D, P0/M, Z1.D, Z3.D

(200) 0x42827c FMUL	Z4.D, Z28.D, Z4.D

(200) 0x428280 MOVPRFX	Z28, Z31

(200) 0x428284 MLA	Z28.D, P0/M, Z23.D, Z30.D

(200) 0x428288 LD1D	{Z28.D}, P0/Z, [X16, Z28.D,LSL #3]

(200) 0x42828c FSUB	Z4.D, Z28.D, Z4.D

(200) 0x428290 MOVPRFX	Z28, Z31

(200) 0x428294 MLA	Z28.D, P0/M, Z24.D, Z30.D

(200) 0x428298 ST1D	{Z4.D}, P0, [X15, Z28.D,LSL #3]

(200) 0x42829c LD1D	{Z3.D}, P0/Z, [X26, Z8.D,LSL #3]

(200) 0x4282a0 LDR	Z4, [X18, #511, MUL VL]

(200) 0x4282a4 ADD	Z0.D, Z0.D, Z4.D

(200) 0x4282a8 FMUL	Z1.D, Z3.D, Z1.D

(200) 0x4282ac MOVPRFX	Z3, Z31

(200) 0x4282b0 MLA	Z3.D, P0/M, Z25.D, Z30.D

(200) 0x4282b4 ST1D	{Z1.D}, P0, [X17, Z3.D,LSL #3]

(200) 0x4282b8 B.NE	428080

0x4282bc CBZ	X12, 428544

0x4282c0 LDP	X1, X5, [SP, #224]

0x4282c4 LDP	X21, X22, [SP, #24]

0x4282c8 STR	X23, [SP, #80]

0x4282cc FMOV	D0, #0.2500000

0x4282d0 FMOV	D1, #-1.0000000

0x4282d4 UBFM	X17, X10, #32, #31

0x4282d8 SBFM	X15, X5, #61, #31

0x4282dc SUB	X8, XZR, X1,LSL #32

0x4282e0 LDP	X18, X16, [SP, #40]

0x4282e4 ADD	X11, X23, X15

0x4282e8 ADD	X12, X25, X15

0x4282ec ADD	X13, X27, X15

0x4282f0 ADD	X14, X20, X15

0x4282f4 ADD	X15, X24, X15

0x4282f8 ADD	X9, X11, #8

0x4282fc ADD	X12, X12, #8

0x428300 ADD	X13, X13, #8

0x428304 ADD	X14, X14, #8

0x428308 ADD	X15, X15, #8

0x42830c STP	X8, X9, [SP, #96]

0x428310 SUB	W8, WZR, W1

0x428314 STR	W8, [SP, #92]

0x428318 LDP	X23, X8, [SP, #56]

0x42831c HINT	#0

(199) 0x428320 SDIV	X3, X10, X1

(199) 0x428324 LDP	X11, X9, [SP, #208]

(199) 0x428328 ADD	W1, W5, W10

(199) 0x42832c ADD	X10, X10, #1

(199) 0x428330 CMP	X0, X10

(199) 0x428334 ADD	W4, W9, W3

(199) 0x428338 LDR	W9, [SP, #92]

(199) 0x42833c MADD	W2, W9, W3, W1

(199) 0x428340 SBFM	X1, X4, #0, #31

(199) 0x428344 ORR	X9, XZR, X6

(199) 0x428348 ADD	W4, W4, #1

(199) 0x42834c MADD	X5, X8, X1, XZR

(199) 0x428350 SBFM	X4, X4, #0, #31

(199) 0x428354 SBFM	X2, X2, #0, #31

(199) 0x428358 ADD	X6, X5, X2

(199) 0x42835c LDR	D2, [X25, X6,LSL #3]

(199) 0x428360 MADD	X6, X8, X4, XZR

(199) 0x428364 ADD	X7, X6, X2

(199) 0x428368 LDR	D3, [X25, X7,LSL #3]

(199) 0x42836c MADD	X7, X23, X1, XZR

(199) 0x428370 ADD	X28, X7, X2

(199) 0x428374 LDR	D4, [X27, X28,LSL #3]

(199) 0x428378 MADD	X28, X23, X4, XZR

(199) 0x42837c ADD	X30, X28, X2

(199) 0x428380 FADD	D2, D2, D3

(199) 0x428384 LDR	D5, [X27, X30,LSL #3]

(199) 0x428388 MADD	X30, X11, X1, XZR

(199) 0x42838c LDR	X11, [SP, #96]

(199) 0x428390 FADD	D2, D2, D4

(199) 0x428394 MADD	X3, X11, X3, X17

(199) 0x428398 LDR	X11, [SP, #80]

(199) 0x42839c ADD	X5, X5, X3,ASR #32

(199) 0x4283a0 FADD	D2, D2, D5

(199) 0x4283a4 LDR	D6, [X12, X5,LSL #3]

(199) 0x4283a8 ADD	X5, X30, X2

(199) 0x4283ac LDR	D7, [X11, X5,LSL #3]

(199) 0x4283b0 ADD	X5, X6, X3,ASR #32

(199) 0x4283b4 ADD	X6, X7, X3,ASR #32

(199) 0x4283b8 LDR	D17, [X13, X6,LSL #3]

(199) 0x4283bc ADD	X6, X28, X3,ASR #32

(199) 0x4283c0 LDR	X28, [SP, #104]

(199) 0x4283c4 LDR	D16, [X12, X5,LSL #3]

(199) 0x4283c8 ADD	X5, X30, X3,ASR #32

(199) 0x4283cc LDR	D18, [X13, X6,LSL #3]

(199) 0x4283d0 MADD	X6, X21, X1, XZR

(199) 0x4283d4 LDR	D19, [X28, X5,LSL #3]

(199) 0x4283d8 ADD	X5, X6, X3,ASR #32

(199) 0x4283dc ADD	X7, X6, X2

(199) 0x4283e0 FMUL	D2, D7, D2

(199) 0x4283e4 LDR	D21, [X14, X5,LSL #3]

(199) 0x4283e8 MADD	X5, X16, X1, XZR

(199) 0x4283ec FADD	D3, D6, D16

(199) 0x4283f0 LDR	D20, [X20, X7,LSL #3]

(199) 0x4283f4 LDR	D6, [X9]

(199) 0x4283f8 FMUL	D2, D2, D0

(199) 0x4283fc ADD	X6, X5, X2

(199) 0x428400 ADD	X5, X5, X3,ASR #32

(199) 0x428404 FADD	D3, D3, D17

(199) 0x428408 LDR	D22, [X24, X6,LSL #3]

(199) 0x42840c MADD	X6, X22, X4, X2

(199) 0x428410 LDR	D24, [X15, X5,LSL #3]

(199) 0x428414 MADD	X5, X21, X4, XZR

(199) 0x428418 MADD	X4, X16, X4, XZR

(199) 0x42841c FADD	D3, D3, D18

(199) 0x428420 LDR	D23, [X19, X6,LSL #3]

(199) 0x428424 ADD	X6, X5, X2

(199) 0x428428 ADD	X5, X5, X3,ASR #32

(199) 0x42842c FMUL	D3, D19, D3

(199) 0x428430 ADD	X3, X4, X3,ASR #32

(199) 0x428434 FADD	D4, D20, D21

(199) 0x428438 FMUL	D2, D6, D2

(199) 0x42843c LDR	D25, [X20, X6,LSL #3]

(199) 0x428440 LDR	D26, [X14, X5,LSL #3]

(199) 0x428444 ADD	X5, X4, X2

(199) 0x428448 ORR	X6, XZR, X9

(199) 0x42844c LDR	X9, [SP, #200]

(199) 0x428450 LDR	D7, [X15, X3,LSL #3]

(199) 0x428454 FMUL	D3, D3, D0

(199) 0x428458 LDR	D27, [X24, X5,LSL #3]

(199) 0x42845c MADD	X5, X22, X1, X2

(199) 0x428460 FADD	D4, D4, D22

(199) 0x428464 LDR	D28, [X19, X5,LSL #3]

(199) 0x428468 MADD	X3, X9, X1, X2

(199) 0x42846c LDR	X9, [SP, #192]

(199) 0x428470 FMUL	D3, D6, D3

(199) 0x428474 FADD	D4, D4, D24

(199) 0x428478 LDR	X5, [SP, #232]

(199) 0x42847c FADD	D5, D25, D26

(199) 0x428480 FSUB	D2, D3, S2

(199) 0x428484 FADD	D5, D5, D27

(199) 0x428488 LDR	D3, [X9, X3,LSL #3]

(199) 0x42848c LDR	X9, [SP, #184]

(199) 0x428490 FADD	D5, D5, D7

(199) 0x428494 FMUL	D4, D28, D4

(199) 0x428498 FMUL	D5, D23, D5

(199) 0x42849c MADD	X3, X9, X1, X2

(199) 0x4284a0 LDR	X9, [SP, #176]

(199) 0x4284a4 FMUL	D4, D4, D0

(199) 0x4284a8 FMUL	D5, D5, D0

(199) 0x4284ac FMUL	D4, D6, D4

(199) 0x4284b0 FMUL	D5, D6, D5

(199) 0x4284b4 LDR	D6, [X9, X3,LSL #3]

(199) 0x4284b8 LDR	X9, [SP, #168]

(199) 0x4284bc FADD	D2, D2, D5

(199) 0x4284c0 FDIV	D5, D1, D3

(199) 0x4284c4 MADD	X3, X9, X1, X2

(199) 0x4284c8 LDR	X9, [SP, #160]

(199) 0x4284cc FSUB	D2, D2, S4

(199) 0x4284d0 LDR	D7, [X26, X3,LSL #3]

(199) 0x4284d4 MADD	X4, X9, X1, X2

(199) 0x4284d8 LDR	X9, [SP, #152]

(199) 0x4284dc LDR	D16, [X9, X4,LSL #3]

(199) 0x4284e0 FDIV	D6, D6, D7

(199) 0x4284e4 LDR	X9, [SP, #128]

(199) 0x4284e8 MADD	X4, X9, X1, X2

(199) 0x4284ec LDR	X9, [SP, #120]

(199) 0x4284f0 FDIV	D4, D16, D7

(199) 0x4284f4 FADD	D4, D6, D4

(199) 0x4284f8 FMUL	D4, D4, D2

(199) 0x4284fc FADD	D2, D3, D2

(199) 0x428500 FDIV	D2, D3, D2

(199) 0x428504 FMUL	D4, D5, D4

(199) 0x428508 LDR	D5, [X9, X4,LSL #3]

(199) 0x42850c LDR	X9, [SP, #144]

(199) 0x428510 MADD	X4, X9, X1, X2

(199) 0x428514 LDR	X9, [SP, #136]

(199) 0x428518 FADD	D4, D5, D4

(199) 0x42851c STR	D4, [X9, X4,LSL #3]

(199) 0x428520 LDR	X9, [SP, #112]

(199) 0x428524 LDR	D4, [X26, X3,LSL #3]

(199) 0x428528 MADD	X1, X9, X1, X2

(199) 0x42852c MOVZ	X9, #1

(199) 0x428530 ADD	X17, X17, X9

(199) 0x428534 FMUL	D2, D4, D2

(199) 0x428538 STR	D2, [X18, X1,LSL #3]

(199) 0x42853c LDR	X1, [SP, #224]

(199) 0x428540 B.NE	428320

0x428544 LDR	W1, [SP, #76]

0x428548 ADRP	X0,

0x42854c ADD	X0, X0, #2472

0x428550 BL	402d80

0x428554 ADDVL	SP, SP, #3

0x428558 ADD	SP, SP, #272

0x42855c LDP	D9, D8, [SP, #48]

0x428560 LDP	D11, D10, [SP, #32]

0x428564 LDP	D13, D12, [SP, #16]

0x428568 LDP	X20, X19, [SP, #144]

0x42856c LDP	X22, X21, [SP, #128]

0x428570 LDP	X24, X23, [SP, #112]

0x428574 LDP	X26, X25, [SP, #96]

0x428578 LDP	X28, X27, [SP, #80]

0x42857c LDP	X29, X30, [SP, #64]

0x428580 LDP	D15, D14, [SP], #160

0x428584 RET

0x428588 HINT	#0

0x42858c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:69-83
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 35.17 to 22.00 cycles (1.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 36% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 35.17 to 33.67 cycles (1.04x speedup).

Details

27% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 35.17 to 1.00 cycles (35.17x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 744 bytes. The binary function is storing 500 bytes.

General properties

nb instructions	196
loop length	784
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

24.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	18.00	18.00	26.00	18.00	3.00	3.00	2.50	2.50	35.17	34.83	35.00	14.00	14.00
cycles	4.00	4.00	18.00	18.00	26.00	18.00	3.00	3.00	2.50	2.50	35.17	34.83	35.00	14.00	14.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	24.13
Overall L1	35.17

Vectorization ratios

INT

all	28%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	27%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 35.17 cycles. At this rate:

22% of peak load performance is reached (21.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
29% of peak store performance is reached (14.22 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 427e20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP D15, D14, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL SP, SP, #61	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W10, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 428554 <.omp_outlined..2+0x734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W21, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 428554 <.omp_outlined..2+0x734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X17, X16, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X1, X18, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X2, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X15, X14, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X5, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X13, X12, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X10, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X11, X10, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X23, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #244]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X17, X5, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X1, X2, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463f00>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X4, X6, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, SP, #264	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X18, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X15, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X16, X17, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W1, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X14, X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X13, X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W11, W9, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UMADDL X28, W11, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X11, X3, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #244	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X12, X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, XZR, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 402ee0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X14, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X9, X8, X28, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X14, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 428544 <.omp_outlined..2+0x724>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X10, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4282c0 <.omp_outlined..2+0x4a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
DUP Z1.D, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FDUP Z27.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
STR Z1, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
UDIV X10, X12, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
LDP X9, X8, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X13, X10, X11, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X10, X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
INDEX Z0.D, X14, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
ADD W14, W22, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z2.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z1, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LDR X9, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
STR Z1, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z26.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD W14, W21, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z6.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z5.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z29.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z7.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X8, X17, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z16.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z17.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z18.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z19.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X9, X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z20.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z21.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X14, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z22.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X8, X15, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z23.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z24.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X8, X16, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z25.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X12, 428544 <.omp_outlined..2+0x724>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X1, X5, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
UBFM X17, X10, #32, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X15, X5, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, XZR, X1,LSL #32	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDP X18, X16, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X11, X23, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X25, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X27, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X20, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X24, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X8, X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, WZR, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #92]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
HINT #0
LDR W1, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463548>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2472	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402d80 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADDVL SP, SP, #3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D15, D14, [SP], #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:69-83
/home/hbollore/qaas-runs/170-290-5445/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

27% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 35.17 to 1.00 cycles (35.17x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 744 bytes. The binary function is storing 500 bytes.

General properties

nb instructions	196
loop length	784
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

24.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	18.00	18.00	26.00	18.00	3.00	3.00	2.50	2.50	35.17	34.83	35.00	14.00	14.00
cycles	4.00	4.00	18.00	18.00	26.00	18.00	3.00	3.00	2.50	2.50	35.17	34.83	35.00	14.00	14.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	24.13
Overall L1	35.17

Vectorization ratios

INT

all	28%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	27%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 35.17 cycles. At this rate:

22% of peak load performance is reached (21.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
29% of peak store performance is reached (14.22 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 427e20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP D15, D14, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL SP, SP, #61	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W10, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 428554 <.omp_outlined..2+0x734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W21, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W9, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 428554 <.omp_outlined..2+0x734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X17, X16, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X1, X18, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X2, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X15, X14, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X5, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X13, X12, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X10, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X11, X10, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X23, [X6, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X7, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #244]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X17, X5, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X1, X2, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X5, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463f00>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X4, X6, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, SP, #264	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X18, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X15, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X16, X17, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W1, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X14, X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X13, X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W11, W9, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UMADDL X28, W11, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X11, X3, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #244	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X12, X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, XZR, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 402ee0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X14, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X9, X8, X28, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X14, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 428544 <.omp_outlined..2+0x724>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X10, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 4282c0 <.omp_outlined..2+0x4a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
DUP Z1.D, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FDUP Z27.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
STR Z1, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
UDIV X10, X12, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
LDP X9, X8, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X13, X10, X11, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X10, X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
INDEX Z0.D, X14, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2
ADD W14, W22, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z2.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR Z1, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LDR X9, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z1.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
STR Z1, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z26.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
ADD W14, W21, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z6.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z5.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z29.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
DUP Z7.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X8, X17, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z16.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z17.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z18.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z19.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X9, X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z20.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z21.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X14, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z22.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X8, X15, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z23.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
DUP Z24.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDP X8, X16, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
DUP Z25.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
LDR X8, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X12, 428544 <.omp_outlined..2+0x724>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X1, X5, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FMOV D0, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
UBFM X17, X10, #32, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X15, X5, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, XZR, X1,LSL #32	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDP X18, X16, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X11, X23, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X25, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X27, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X20, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X24, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X8, X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W8, WZR, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #92]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
HINT #0
LDR W1, [SP, #76]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <463548>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #2472	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402d80 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADDVL SP, SP, #3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD SP, SP, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D15, D14, [SP], #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..2#0x427e20–	7.87	10.51
○Loop 200 - PdV.cpp:69-83 - exec	7.87	10.47
○Loop 199 - PdV.cpp:70-83 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code