OV - exec - Function .omp

	Function: .omp_outlined..92	Module: exec	Source: update_halo.cpp:537-540	Coverage: 0.01%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 537 - 540

--------------------------------------------------------------------------------

537: #pragma omp parallel for simd

538:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

539:         for (int j = 0; j < depth; ++j) {

540:           field.vol_flux_x(1 - j, k) = -field.vol_flux_x(1 + 2 + j, k);

0x430e40 SUB	SP, SP, #128

0x430e44 STP	X29, X30, [SP, #32]

0x430e48 STP	X28, X27, [SP, #48]

0x430e4c STP	X26, X25, [SP, #64]

0x430e50 STP	X24, X23, [SP, #80]

0x430e54 STP	X22, X21, [SP, #96]

0x430e58 STP	X20, X19, [SP, #112]

0x430e5c ADD	X29, SP, #32

0x430e60 LDR	W22, [X2]

0x430e64 LDR	W20, [X3]

0x430e68 LDR	W8, [X4]

0x430e6c SUB	W9, W22, W20

0x430e70 ADD	W8, W8, W20

0x430e74 SUBS	W24, W8, W9

0x430e78 B.LT	430ef0

0x430e7c LDR	W19, [X0]

0x430e80 LDR	X23, [X5, #264]

0x430e84 LDR	X21, [X5, #280]

0x430e88 MOVZ	W8, #1

0x430e8c ADRP	X0,

0x430e90 ADD	X0, X0, #1952

0x430e94 ADD	X3, SP, #16

0x430e98 SUB	X4, X29, #4

0x430e9c STP	W24, WZR, [X29, #504]

0x430ea0 SUB	X5, X29, #8

0x430ea4 SUB	X6, X29, #12

0x430ea8 MOVZ	W2, #34

0x430eac STUR	W8, [X29, #500]

0x430eb0 STR	WZR, [SP, #16]

0x430eb4 STR	W8, [SP]

0x430eb8 MOVZ	W7, #1

0x430ebc ORR	W1, WZR, W19

0x430ec0 BL	402f40

0x430ec4 LDP	W8, W9, [X29, #504]

0x430ec8 CMP	W8, W24

0x430ecc CSEL	W8, W8, W24, #3

0x430ed0 ADD	W10, W8, #1

0x430ed4 CMP	W9, W10

0x430ed8 CCMP	W20, #1, #8, #3

0x430edc B.GE	430f10

(629) 0x430ee0 ORR	W1, WZR, W19

(629) 0x430ee4 ADRP	X0,

(629) 0x430ee8 ADD	X0, X0, #1976

(629) 0x430eec BL	402d80

(629) 0x430ef0 LDP	X20, X19, [SP, #112]

(629) 0x430ef4 LDP	X22, X21, [SP, #96]

(629) 0x430ef8 LDP	X24, X23, [SP, #80]

(629) 0x430efc LDP	X26, X25, [SP, #64]

(629) 0x430f00 LDP	X28, X27, [SP, #48]

(629) 0x430f04 LDP	X29, X30, [SP, #32]

(629) 0x430f08 ADD	SP, SP, #128

(629) 0x430f0c RET

(629) 0x430f10 ADD	X15, X21, #24

(629) 0x430f14 UBFM	X16, X20, #61, #60

(629) 0x430f18 ADD	W14, W9, W22

(629) 0x430f1c ADD	X6, X21, #16

(629) 0x430f20 MOVZ	W0, #12

(629) 0x430f24 RDVL	X5, #1

(629) 0x430f28 SUB	X11, X20, #1

(629) 0x430f2c ORR	W10, WZR, WZR

(629) 0x430f30 RDVL	X18, #2

(629) 0x430f34 RDVL	X1, #62

(629) 0x430f38 ADD	X2, X15, X16

(629) 0x430f3c ADD	X12, X21, #8

(629) 0x430f40 UBFM	X13, X23, #61, #60

(629) 0x430f44 SUB	X16, X21, X16

(629) 0x430f48 SUB	X17, XZR, X11,LSL #3

(629) 0x430f4c ADD	X3, X16, #16

(629) 0x430f50 CNTW	X16, ALL

(629) 0x430f54 CMP	X16, #12

(629) 0x430f58 SUB	W14, W14, W20

(629) 0x430f5c ADD	W14, W14, #1

(629) 0x430f60 ADDVL	X4, X15, #1

(629) 0x430f64 SUB	X5, X6, X5

(629) 0x430f68 CSEL	X0, X16, X0, #8

(629) 0x430f6c CMP	X15, X6

(629) 0x430f70 ADDVL	X6, X6, #62

(629) 0x430f74 CCMP	X3, X2, #2, #3

(629) 0x430f78 PTRUE	P0.B, ALL

(629) 0x430f7c PTRUE	P1.D, ALL

(629) 0x430f80 ADD	X3, X21, #48

(629) 0x430f84 CSINC	W2, WZR, WZR, #2

(629) 0x430f88 ORR	W7, WZR, W14

(629) 0x430f8c B	430fb4

0x430f90 HINT	#0

0x430f94 HINT	#0

0x430f98 HINT	#0

0x430f9c HINT	#0

(629) 0x430fa0 CMP	W9, W8

(629) 0x430fa4 ADD	W9, W9, #1

(629) 0x430fa8 ADD	W10, W10, #1

(629) 0x430fac ADD	W7, W7, #1

(629) 0x430fb0 B.EQ	430ee0

(629) 0x430fb4 SBFM	X22, X7, #0, #31

(629) 0x430fb8 CMP	X0, X20

(629) 0x430fbc MADD	X22, X13, X22, XZR

(629) 0x430fc0 B.HI	430fe4

(629) 0x430fc4 ADD	W23, W14, W10

(629) 0x430fc8 ANDS	XZR, X11, #4227

(629) 0x430fcc SBFM	X23, X23, #0, #31

(629) 0x430fd0 MADD	X23, X13, X23, X12

(629) 0x430fd4 ADD	X24, X23, X17

(629) 0x430fd8 CCMP	X24, X23, #2, #0

(629) 0x430fdc CSINC	W23, W2, WZR, #9

(629) 0x430fe0 TBZ	W23, #0, 431088

(629) 0x430fe4 ORR	X23, XZR, XZR

(629) 0x430fe8 SUB	W24, W20, W23

(629) 0x430fec ANDS	X25, X24, #4160

(629) 0x430ff0 ORR	X24, XZR, X23

(629) 0x430ff4 B.EQ	431020

(629) 0x430ff8 SUB	X24, X22, X23,LSL #3

(629) 0x430ffc ADD	X26, X15, X22

(629) 0x431000 ADD	X27, X12, X24

(629) 0x431004 ORR	X24, XZR, X23

  (631) 0x431008 LDR	D0, [X26, X24,LSL #3]

  (631) 0x43100c ADD	X24, X24, #1

  (631) 0x431010 SUBS	X25, X25, #1

  (631) 0x431014 FNEG	D0, D0

  (631) 0x431018 STR	D0, [X27], #504

  (631) 0x43101c B.NE	431008

(629) 0x431020 ORN	X23, XZR, X23

(629) 0x431024 ADD	X23, X23, X20

(629) 0x431028 CMP	X23, #3

(629) 0x43102c B.CC	430fa0

(629) 0x431030 UBFM	X25, X24, #61, #60

(629) 0x431034 SUB	X24, X20, X24

(629) 0x431038 ADD	X23, X22, X25

(629) 0x43103c SUB	X22, X22, X25

(629) 0x431040 ADD	X23, X3, X23

(629) 0x431044 ADD	X22, X21, X22

  (630) 0x431048 LDUR	D0, [X23, #488]

  (630) 0x43104c SUBS	X24, X24, #4

  (630) 0x431050 FNEG	D0, D0

  (630) 0x431054 STR	D0, [X22, #8]

  (630) 0x431058 LDUR	D0, [X23, #496]

  (630) 0x43105c FNEG	D0, D0

  (630) 0x431060 STR	D0, [X22]

  (630) 0x431064 LDUR	D0, [X23, #504]

  (630) 0x431068 FNEG	D0, D0

  (630) 0x43106c STUR	D0, [X22, #504]

  (630) 0x431070 LDR	D0, [X23], #32

  (630) 0x431074 FNEG	D0, D0

  (630) 0x431078 STUR	D0, [X22, #496]

  (630) 0x43107c SUB	X22, X22, #32

  (630) 0x431080 B.NE	431048

(629) 0x431084 B	430fa0

(629) 0x431088 UDIV	X23, X20, X16

(629) 0x43108c ORR	X26, XZR, X6

(629) 0x431090 ORR	X27, XZR, X5

(629) 0x431094 ORR	X28, XZR, X4

(629) 0x431098 ORR	X30, XZR, X15

(629) 0x43109c UMSUBL	X24, W23, W16, X20

(629) 0x4310a0 UMADDL	X23, W23, W16, XZR

(629) 0x4310a4 ORR	X25, XZR, X23

  (632) 0x4310a8 LD1B	{Z0.B}, P0/Z, [X30, X22]

  (632) 0x4310ac LD1B	{Z1.B}, P0/Z, [X28, X22]

  (632) 0x4310b0 ADD	X30, X30, X18

  (632) 0x4310b4 ADD	X28, X28, X18

  (632) 0x4310b8 SUBS	X25, X25, X16

  (632) 0x4310bc FNEG	Z0.D, P1/M, Z0.D

  (632) 0x4310c0 FNEG	Z1.D, P1/M, Z1.D

  (632) 0x4310c4 REV	Z0.D, Z0.D

  (632) 0x4310c8 ST1B	{Z0.B}, P0, [X27, X22]

  (632) 0x4310cc REV	Z0.D, Z1.D

  (632) 0x4310d0 ADD	X27, X27, X1

  (632) 0x4310d4 ST1B	{Z0.B}, P0, [X26, X22]

  (632) 0x4310d8 ADD	X26, X26, X1

  (632) 0x4310dc B.NE	4310a8

(629) 0x4310e0 CBNZ	X24, 430fe8

0x4310e4 B	430fa0

0x4310e8 HINT	#0

0x4310ec HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:537-540
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:537-540.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.67 to 0.71 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	47
loop length	188
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 430e40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 430ef0 <.omp_outlined..92+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464e8c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1952	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 430f10 <.omp_outlined..92+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
B 430fa0 <.omp_outlined..92+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	update_halo.cpp:537-540
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:537-540.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	47
loop length	188
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 430e40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 430ef0 <.omp_outlined..92+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464e8c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1952	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 430f10 <.omp_outlined..92+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
B 430fa0 <.omp_outlined..92+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..92–	0.01	0
▼Loop 629 - update_halo.cpp:537-540 - exec–	0	0
○Loop 631 - update_halo.cpp:539-540 - exec	0.01	0
○Loop 632 - update_halo.cpp:539-540 - exec	0	0
○Loop 630 - update_halo.cpp:539-540 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code