OV - exec - Function .omp

	Function: .omp_outlined..90	Module: exec	Source: update_halo.cpp:527-530	Coverage: 0.01%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 527 - 530

--------------------------------------------------------------------------------

527: #pragma omp parallel for simd

528:       for (int j = (x_min - depth + 1); j < (x_max + 1 + depth + 2); j++) {

529:         for (int k = 0; k < depth; ++k) {

530:           field.vol_flux_x(j, y_max + 2 + k) = field.vol_flux_x(j, y_max - k);

0x430c00 SUB	SP, SP, #144

0x430c04 STP	X29, X30, [SP, #48]

0x430c08 STP	X28, X27, [SP, #64]

0x430c0c STP	X26, X25, [SP, #80]

0x430c10 STP	X24, X23, [SP, #96]

0x430c14 STP	X22, X21, [SP, #112]

0x430c18 STP	X20, X19, [SP, #128]

0x430c1c ADD	X29, SP, #48

0x430c20 LDR	W20, [X3]

0x430c24 LDR	W8, [X4]

0x430c28 LDR	W24, [X2]

0x430c2c ADD	W8, W20, W8

0x430c30 SUB	W9, W24, W20

0x430c34 ADD	W8, W8, #1

0x430c38 SUBS	W19, W8, W9

0x430c3c B.LT	430cb4

0x430c40 LDR	W1, [X0]

0x430c44 LDR	X23, [X5, #264]

0x430c48 LDR	X21, [X5, #280]

0x430c4c MOVZ	W8, #1

0x430c50 ADRP	X0,

0x430c54 ADD	X0, X0, #1880

0x430c58 SUB	X3, X29, #16

0x430c5c SUB	X4, X29, #4

0x430c60 LDRSW	X22, [X6]

0x430c64 SUB	X5, X29, #8

0x430c68 SUB	X6, X29, #12

0x430c6c MOVZ	W2, #34

0x430c70 STP	W19, WZR, [X29, #504]

0x430c74 STP	WZR, W8, [X29, #496]

0x430c78 STR	W8, [SP]

0x430c7c MOVZ	W7, #1

0x430c80 STR	W1, [SP, #20]

0x430c84 BL	402f40

0x430c88 LDP	W8, W9, [X29, #504]

0x430c8c CMP	W8, W19

0x430c90 CSEL	W8, W8, W19, #3

0x430c94 ADD	W10, W8, #1

0x430c98 CMP	W9, W10

0x430c9c CCMP	W20, #1, #8, #3

0x430ca0 B.GE	430cd4

(626) 0x430ca4 LDR	W1, [SP, #20]

(626) 0x430ca8 ADRP	X0,

(626) 0x430cac ADD	X0, X0, #1904

(626) 0x430cb0 BL	402d80

(626) 0x430cb4 LDP	X20, X19, [SP, #128]

(626) 0x430cb8 LDP	X22, X21, [SP, #112]

(626) 0x430cbc LDP	X24, X23, [SP, #96]

(626) 0x430cc0 LDP	X26, X25, [SP, #80]

(626) 0x430cc4 LDP	X28, X27, [SP, #64]

(626) 0x430cc8 LDP	X29, X30, [SP, #48]

(626) 0x430ccc ADD	SP, SP, #144

(626) 0x430cd0 RET

(626) 0x430cd4 SUB	X11, X22, #2

(626) 0x430cd8 ADD	W10, W22, #2

(626) 0x430cdc SUB	X12, X22, #1

(626) 0x430ce0 UBFM	X15, X23, #59, #58

(626) 0x430ce4 UBFM	X4, X23, #61, #60

(626) 0x430ce8 AND	X14, X20, #6014

(626) 0x430cec MADD	X11, X23, X11, XZR

(626) 0x430cf0 SBFM	X10, X10, #0, #31

(626) 0x430cf4 MADD	X13, X23, X12, XZR

(626) 0x430cf8 SUB	X16, XZR, X15

(626) 0x430cfc SUB	X5, XZR, X4

(626) 0x430d00 AND	X12, X20, #4160

(626) 0x430d04 ADD	X11, X21, X11,LSL #3

(626) 0x430d08 ADD	X17, X21, X13,LSL #3

(626) 0x430d0c STR	X11, [SP, #24]

(626) 0x430d10 ADD	X11, X10, #2

(626) 0x430d14 MADD	X11, X23, X11, XZR

(626) 0x430d18 ADD	X19, X21, X11,LSL #3

(626) 0x430d1c ADD	W11, W9, W24

(626) 0x430d20 SUB	W11, W11, W20

(626) 0x430d24 ADD	W7, W11, #1

(626) 0x430d28 MADD	X11, X23, X10, XZR

(626) 0x430d2c ADD	X13, X23, X11

(626) 0x430d30 ADD	X2, X21, X11,LSL #3

(626) 0x430d34 MADD	X11, X23, X22, XZR

(626) 0x430d38 ADD	X18, X21, X13,LSL #3

(626) 0x430d3c SUB	X13, X22, #3

(626) 0x430d40 ADD	X3, X21, X11,LSL #3

(626) 0x430d44 MADD	X13, X23, X13, XZR

(626) 0x430d48 ADD	X0, X21, X13,LSL #3

(626) 0x430d4c ADD	X13, X10, #3

(626) 0x430d50 MADD	X13, X23, X13, XZR

(626) 0x430d54 ADD	X1, X21, X13,LSL #3

(626) 0x430d58 B	430d70

0x430d5c HINT	#0

(626) 0x430d60 CMP	W9, W8

(626) 0x430d64 ADD	W9, W9, #1

(626) 0x430d68 ADD	W7, W6, #1

(626) 0x430d6c B.EQ	430ca4

(626) 0x430d70 SBFM	X6, X7, #0, #31

(626) 0x430d74 CMP	W20, #4

(626) 0x430d78 B.CS	430d84

(626) 0x430d7c ORR	X23, XZR, XZR

(626) 0x430d80 B	430df4

(626) 0x430d84 LDR	X11, [SP, #24]

(626) 0x430d88 ORR	X23, XZR, XZR

(626) 0x430d8c ORR	X24, XZR, X3

(626) 0x430d90 ORR	X25, XZR, X2

(626) 0x430d94 ORR	X26, XZR, X1

(626) 0x430d98 ORR	X27, XZR, X0

(626) 0x430d9c ORR	X28, XZR, X18

(626) 0x430da0 ORR	X30, XZR, X17

(626) 0x430da4 ORR	X13, XZR, X19

  (625) 0x430da8 LDR	D0, [X24, X6,LSL #3]

  (625) 0x430dac ADD	X23, X23, #4

  (625) 0x430db0 ADD	X24, X24, X16

  (625) 0x430db4 CMP	X14, X23

  (625) 0x430db8 STR	D0, [X25, X6,LSL #3]

  (625) 0x430dbc ADD	X25, X25, X15

  (625) 0x430dc0 LDR	D0, [X30, X6,LSL #3]

  (625) 0x430dc4 ADD	X30, X30, X16

  (625) 0x430dc8 STR	D0, [X28, X6,LSL #3]

  (625) 0x430dcc ADD	X28, X28, X15

  (625) 0x430dd0 LDR	D0, [X11, X6,LSL #3]

  (625) 0x430dd4 ADD	X11, X11, X16

  (625) 0x430dd8 STR	D0, [X13, X6,LSL #3]

  (625) 0x430ddc ADD	X13, X13, X15

  (625) 0x430de0 LDR	D0, [X27, X6,LSL #3]

  (625) 0x430de4 ADD	X27, X27, X16

  (625) 0x430de8 STR	D0, [X26, X6,LSL #3]

  (625) 0x430dec ADD	X26, X26, X15

  (625) 0x430df0 B.NE	430da8

(626) 0x430df4 CBZ	X12, 430d60

0x430df8 SBFM	X13, X7, #61, #31

0x430dfc ADD	X11, X10, X23

0x430e00 SUB	X7, X22, X23

0x430e04 MADD	X11, X4, X11, X13

0x430e08 MADD	X13, X4, X7, X13

0x430e0c ORR	X7, XZR, X12

0x430e10 ADD	X11, X21, X11

0x430e14 ADD	X13, X21, X13

0x430e18 HINT	#0

0x430e1c HINT	#0

(624) 0x430e20 LDR	D0, [X13]

(624) 0x430e24 ADD	X13, X13, X5

(624) 0x430e28 SUBS	X7, X7, #1

(624) 0x430e2c STR	D0, [X11]

(624) 0x430e30 ADD	X11, X11, X4

(624) 0x430e34 B.NE	430e20

0x430e38 B	430d60

0x430e3c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:527-530
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:527-530.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 16% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 7.25 to 1.06 cycles (6.82x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.25 to 0.50 cycles (14.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	54
loop length	216
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	6.00	6.00	6.00	5.00	5.00
cycles	2.00	2.00	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	6.00	6.00	6.00	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.25 cycles. At this rate:

6% of peak load performance is reached (6.07 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
34% of peak store performance is reached (16.55 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 430c00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W24, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W24, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W19, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 430cb4 <.omp_outlined..90+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464c50>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1880	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRSW X22, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W19, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 430cd4 <.omp_outlined..90+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
SBFM X13, X7, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X10, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X7, X22, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X4, X11, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X13, X4, X7, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X7, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X21, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X21, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
B 430d60 <.omp_outlined..90+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	update_halo.cpp:527-530
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:527-530.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.25 to 0.50 cycles (14.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	54
loop length	216
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	6.00	6.00	6.00	5.00	5.00
cycles	2.00	2.00	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	6.00	6.00	6.00	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.25 cycles. At this rate:

6% of peak load performance is reached (6.07 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
34% of peak store performance is reached (16.55 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 430c00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W24, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W24, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W19, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 430cb4 <.omp_outlined..90+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464c50>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1880	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDRSW X22, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W19, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W1, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 430cd4 <.omp_outlined..90+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
SBFM X13, X7, #61, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X10, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X7, X22, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X4, X11, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X13, X4, X7, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X7, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X21, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X21, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
B 430d60 <.omp_outlined..90+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..90–	0.01	0
▼Loop 626 - update_halo.cpp:527-530 - exec–	0.01	0
○Loop 625 - update_halo.cpp:529-530 - exec	0	0
○Loop 624 - update_halo.cpp:529-530 - exec	0	0

Report Configuration

Vectorization

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Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code