OV - exec - Function .omp

	Function: .omp_outlined..78	Module: exec	Source: update_halo.cpp:461-464 [...]	Coverage: 0.01%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 461 - 464

--------------------------------------------------------------------------------

461: #pragma omp parallel for simd

462:       for (int k = (y_min - depth + 1); k < (y_max + 1 + depth + 2); k++) {

463:         for (int j = 0; j < depth; ++j) {

464:           field.yvel0(x_max + 2 + 1 + j, k) = field.yvel0(x_max + 1 - j, k);

0x42fda0 SUB	SP, SP, #144

0x42fda4 STP	X29, X30, [SP, #48]

0x42fda8 STP	X28, X27, [SP, #64]

0x42fdac STP	X26, X25, [SP, #80]

0x42fdb0 STP	X24, X23, [SP, #96]

0x42fdb4 STP	X22, X21, [SP, #112]

0x42fdb8 STP	X20, X19, [SP, #128]

0x42fdbc ADD	X29, SP, #48

0x42fdc0 LDR	W20, [X3]

0x42fdc4 LDR	W8, [X4]

0x42fdc8 LDR	W25, [X2]

0x42fdcc ADD	W8, W20, W8

0x42fdd0 SUB	W21, W25, W20

0x42fdd4 ADD	W8, W8, #1

0x42fdd8 SUBS	W26, W8, W21

0x42fddc B.LT	42fe54

0x42fde0 LDR	W19, [X0]

0x42fde4 LDR	X22, [X5, #216]

0x42fde8 LDR	X23, [X5, #232]

0x42fdec MOVZ	W8, #1

0x42fdf0 ADRP	X0,

0x42fdf4 ADD	X0, X0, #1448

0x42fdf8 SUB	X3, X29, #16

0x42fdfc SUB	X4, X29, #4

0x42fe00 LDR	W24, [X6]

0x42fe04 SUB	X5, X29, #8

0x42fe08 SUB	X6, X29, #12

0x42fe0c MOVZ	W2, #34

0x42fe10 STP	W26, WZR, [X29, #504]

0x42fe14 STP	WZR, W8, [X29, #496]

0x42fe18 STR	W8, [SP]

0x42fe1c MOVZ	W7, #1

0x42fe20 ORR	W1, WZR, W19

0x42fe24 BL	402f40

0x42fe28 LDP	W8, W9, [X29, #504]

0x42fe2c CMP	W8, W26

0x42fe30 CSEL	W8, W8, W26, #3

0x42fe34 ADD	W10, W8, #1

0x42fe38 CMP	W9, W10

0x42fe3c CCMP	W20, #1, #8, #3

0x42fe40 B.GE	42fe74

(593) 0x42fe44 ORR	W1, WZR, W19

(593) 0x42fe48 ADRP	X0,

(593) 0x42fe4c ADD	X0, X0, #1472

(593) 0x42fe50 BL	402d80

(593) 0x42fe54 LDP	X20, X19, [SP, #128]

(593) 0x42fe58 LDP	X22, X21, [SP, #112]

(593) 0x42fe5c LDP	X24, X23, [SP, #96]

(593) 0x42fe60 LDP	X26, X25, [SP, #80]

(593) 0x42fe64 LDP	X28, X27, [SP, #64]

(593) 0x42fe68 LDP	X29, X30, [SP, #48]

(593) 0x42fe6c ADD	SP, SP, #144

(593) 0x42fe70 RET

(593) 0x42fe74 ADD	W11, W24, #1

(593) 0x42fe78 UBFM	X18, X20, #61, #60

(593) 0x42fe7c ADD	W15, W24, #3

(593) 0x42fe80 SUB	X0, X20, #1

(593) 0x42fe84 ADD	W14, W9, W25

(593) 0x42fe88 ORR	W10, WZR, WZR

(593) 0x42fe8c PTRUE	P0.D, ALL

(593) 0x42fe90 UBFM	X13, X22, #61, #60

(593) 0x42fe94 SBFM	X16, X11, #61, #31

(593) 0x42fe98 ADD	X1, X23, X18

(593) 0x42fe9c SBFM	X17, X15, #61, #31

(593) 0x42fea0 ADD	X12, X23, X16

(593) 0x42fea4 STP	X12, X11, [SP, #16]

(593) 0x42fea8 ADD	X16, X16, #8

(593) 0x42feac ADD	X15, X23, X17

(593) 0x42feb0 ADD	X1, X1, X17

(593) 0x42feb4 SUB	X17, X16, X18

(593) 0x42feb8 ADD	X3, X23, X16

(593) 0x42febc CNTW	X16, ALL

(593) 0x42fec0 CMP	X16, #28

(593) 0x42fec4 ADD	X2, X23, X17

(593) 0x42fec8 MOVZ	W17, #28

(593) 0x42fecc SUB	W18, W11, W0

(593) 0x42fed0 CSEL	X17, X16, X17, #8

(593) 0x42fed4 ANDS	XZR, X0, #6112

(593) 0x42fed8 SUB	W14, W14, W20

(593) 0x42fedc ADD	W12, W14, #1

(593) 0x42fee0 SUB	X0, XZR, X0,LSL #3

(593) 0x42fee4 CCMP	W18, W11, #0, #0

(593) 0x42fee8 ADD	X11, X15, #16

(593) 0x42feec ORR	W5, WZR, W12

(593) 0x42fef0 STR	X11, [SP, #8]

(593) 0x42fef4 CNTD	X11, ALL

(593) 0x42fef8 CSINC	W18, WZR, WZR, #13

(593) 0x42fefc CMP	X15, X3

(593) 0x42ff00 MOVZ	W3, #1

(593) 0x42ff04 CCMP	X2, X1, #2, #3

(593) 0x42ff08 ORR	W2, WZR, W12

(593) 0x42ff0c SUB	X4, X3, X11

(593) 0x42ff10 CSINC	W1, WZR, WZR, #2

(593) 0x42ff14 B	42ff34

0x42ff18 HINT	#0

0x42ff1c HINT	#0

(593) 0x42ff20 CMP	W9, W8

(593) 0x42ff24 ORR	W9, WZR, W6

(593) 0x42ff28 ADD	W10, W10, #1

(593) 0x42ff2c ADD	W5, W5, #1

(593) 0x42ff30 B.EQ	42fe44

(593) 0x42ff34 ADD	W6, W9, #1

(593) 0x42ff38 SBFM	X25, X5, #0, #31

(593) 0x42ff3c CMP	X17, X20

(593) 0x42ff40 ADD	W3, W6, W21

(593) 0x42ff44 MADD	X26, X13, X25, X15

(593) 0x42ff48 SBFM	X3, X3, #0, #31

(593) 0x42ff4c MADD	X3, X22, X3, XZR

(593) 0x42ff50 ADD	X7, X23, X3,LSL #3

(593) 0x42ff54 B.LS	42ff60

(593) 0x42ff58 ORR	X27, XZR, XZR

(593) 0x42ff5c B	43002c

(593) 0x42ff60 LDR	X12, [SP, #16]

(593) 0x42ff64 ADD	W3, W2, W10

(593) 0x42ff68 ORR	W14, WZR, W19

(593) 0x42ff6c SBFM	X3, X3, #0, #31

(593) 0x42ff70 MADD	X3, X13, X3, X12

(593) 0x42ff74 ADD	X19, X3, X0

(593) 0x42ff78 CMP	X19, X3

(593) 0x42ff7c CSINC	W3, W18, WZR, #9

(593) 0x42ff80 ORR	W3, W3, W1

(593) 0x42ff84 TBZ	W3, #0, 42ffa0

0x42ff88 ORR	X27, XZR, XZR

0x42ff8c ORR	W19, WZR, W14

0x42ff90 B	43002c

0x42ff94 HINT	#0

0x42ff98 HINT	#0

0x42ff9c HINT	#0

(593) 0x42ffa0 UDIV	X3, X20, X16

(593) 0x42ffa4 CNTD	X12, ALL

(593) 0x42ffa8 ORR	W11, WZR, W1

(593) 0x42ffac ORR	X1, XZR, X0

(593) 0x42ffb0 ORR	W0, WZR, W18

(593) 0x42ffb4 ORR	W18, WZR, W2

(593) 0x42ffb8 ORR	W2, WZR, W24

(593) 0x42ffbc ORR	X28, XZR, XZR

(593) 0x42ffc0 ADDVL	X19, X26, #1

(593) 0x42ffc4 UMSUBL	X30, W3, W16, X20

(593) 0x42ffc8 UMADDL	X27, W3, W16, XZR

(593) 0x42ffcc SUB	X3, XZR, X12

(593) 0x42ffd0 LDR	X12, [SP, #24]

(593) 0x42ffd4 ORR	W24, WZR, W12

(593) 0x42ffd8 HINT	#0

(593) 0x42ffdc HINT	#0

  (592) 0x42ffe0 ADD	X12, X7, W24,SXTW #3

  (592) 0x42ffe4 SUB	W24, W24, W16

  (592) 0x42ffe8 ADD	X12, X12, X4,LSL #3

  (592) 0x42ffec LD1D	{Z0.D}, P0/Z, [X12, MUL VL]

  (592) 0x42fff0 LD1D	{Z1.D}, P0/Z, [X12, X3,LSL #3]

  (592) 0x42fff4 REV	Z0.D, Z0.D

  (592) 0x42fff8 REV	Z1.D, Z1.D

  (592) 0x42fffc ST1D	{Z0.D}, P0, [X26, X28,LSL #3]

  (592) 0x430000 ST1D	{Z1.D}, P0, [X19, X28,LSL #3]

  (592) 0x430004 ADD	X28, X28, X16

  (592) 0x430008 CMP	X27, X28

  (592) 0x43000c B.NE	42ffe0

(593) 0x430010 ORR	W24, WZR, W2

(593) 0x430014 ORR	W19, WZR, W14

(593) 0x430018 ORR	W2, WZR, W18

(593) 0x43001c ORR	W18, WZR, W0

(593) 0x430020 ORR	X0, XZR, X1

(593) 0x430024 ORR	W1, WZR, W11

(593) 0x430028 CBZ	X30, 42ff20

(593) 0x43002c SUB	W12, W20, W27

(593) 0x430030 ORR	X28, XZR, X27

(593) 0x430034 ANDS	X30, X12, #4160

(593) 0x430038 B.EQ	430060

(593) 0x43003c LDR	X12, [SP, #24]

(593) 0x430040 ORR	X28, XZR, X27

(593) 0x430044 SUB	W3, W12, W27

  (595) 0x430048 LDR	D0, [X7, X3,SXTW #3]

  (595) 0x43004c SUB	W3, W3, #1

  (595) 0x430050 SUBS	X30, X30, #1

  (595) 0x430054 STR	D0, [X26, X28,LSL #3]

  (595) 0x430058 ADD	X28, X28, #1

  (595) 0x43005c B.NE	430048

(593) 0x430060 ORN	X12, XZR, X27

(593) 0x430064 ADD	X12, X12, X20

(593) 0x430068 CMP	X12, #3

(593) 0x43006c B.CC	42ff20

0x430070 MADD	X12, X13, X25, XZR

0x430074 LDR	X14, [SP, #8]

0x430078 SUB	X25, X20, X28

0x43007c SUB	W26, W24, W28

0x430080 ADD	X12, X12, X28,LSL #3

0x430084 ADD	X27, X14, X12

(594) 0x430088 ADD	W12, W26, #1

(594) 0x43008c SUB	X25, X25, #4

(594) 0x430090 LDR	D0, [X7, X12,SXTW #3]

(594) 0x430094 SUB	W12, W26, #1

(594) 0x430098 STUR	D0, [X27, #496]

(594) 0x43009c LDR	D0, [X7, X26,SXTW #3]

(594) 0x4300a0 STUR	D0, [X27, #504]

(594) 0x4300a4 LDR	D0, [X7, X12,SXTW #3]

(594) 0x4300a8 SUB	W12, W26, #2

(594) 0x4300ac SUB	W26, W26, #4

(594) 0x4300b0 STR	D0, [X27]

(594) 0x4300b4 LDR	D0, [X7, X12,SXTW #3]

(594) 0x4300b8 STR	D0, [X27, #8]

(594) 0x4300bc ADD	X27, X27, #32

(594) 0x4300c0 CBNZ	X25, 430088

0x4300c4 B	42ff20

0x4300c8 HINT	#0

0x4300cc HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:461-464
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:461-464

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 7.25 to 0.94 cycles (7.73x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.25 to 0.50 cycles (14.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	58
loop length	232
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	2.50	2.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Overall L1	7.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.25 cycles. At this rate:

7% of peak load performance is reached (7.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42fda0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42fe54 <.omp_outlined..78+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464df0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42fe74 <.omp_outlined..78+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 43002c <.omp_outlined..78+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
MADD X12, X13, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42ff20 <.omp_outlined..78+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	update_halo.cpp:461-464
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:461-464

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.25 to 0.50 cycles (14.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	58
loop length	232
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	2.50	2.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Overall L1	7.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.25 cycles. At this rate:

7% of peak load performance is reached (7.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42fda0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42fe54 <.omp_outlined..78+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464df0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1448	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42fe74 <.omp_outlined..78+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 43002c <.omp_outlined..78+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
MADD X12, X13, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42ff20 <.omp_outlined..78+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..78–	0.01	0
▼Loop 593 - update_halo.cpp:461-464 - exec–	0	0
○Loop 595 - update_halo.cpp:463-464 - exec	0.01	0
○Loop 592 - update_halo.cpp:463-464 - exec	0	0
○Loop 594 - update_halo.cpp:463-464 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code