OV - exec - Function .omp

	Function: .omp_outlined..70	Module: exec	Source: update_halo.cpp:418-421 [...]	Coverage: 0.01%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 418 - 421

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418: #pragma omp parallel for simd

419:       for (int k = (y_min - depth + 1); k < (y_max + 1 + depth + 2); k++) {

420:         for (int j = 0; j < depth; ++j) {

421:           field.xvel1(x_max + 2 + 1 + j, k) = -field.xvel1(x_max + 1 - j, k);

0x42f450 SUB	SP, SP, #144

0x42f454 STP	X29, X30, [SP, #48]

0x42f458 STP	X28, X27, [SP, #64]

0x42f45c STP	X26, X25, [SP, #80]

0x42f460 STP	X24, X23, [SP, #96]

0x42f464 STP	X22, X21, [SP, #112]

0x42f468 STP	X20, X19, [SP, #128]

0x42f46c ADD	X29, SP, #48

0x42f470 LDR	W20, [X3]

0x42f474 LDR	W8, [X4]

0x42f478 LDR	W25, [X2]

0x42f47c ADD	W8, W20, W8

0x42f480 SUB	W21, W25, W20

0x42f484 ADD	W8, W8, #1

0x42f488 SUBS	W26, W8, W21

0x42f48c B.LT	42f504

0x42f490 LDR	W19, [X0]

0x42f494 LDR	X22, [X5, #192]

0x42f498 LDR	X23, [X5, #208]

0x42f49c MOVZ	W8, #1

0x42f4a0 ADRP	X0,

0x42f4a4 ADD	X0, X0, #1160

0x42f4a8 SUB	X3, X29, #16

0x42f4ac SUB	X4, X29, #4

0x42f4b0 LDR	W24, [X6]

0x42f4b4 SUB	X5, X29, #8

0x42f4b8 SUB	X6, X29, #12

0x42f4bc MOVZ	W2, #34

0x42f4c0 STP	W26, WZR, [X29, #504]

0x42f4c4 STP	WZR, W8, [X29, #496]

0x42f4c8 STR	W8, [SP]

0x42f4cc MOVZ	W7, #1

0x42f4d0 ORR	W1, WZR, W19

0x42f4d4 BL	402f40

0x42f4d8 LDP	W8, W9, [X29, #504]

0x42f4dc CMP	W8, W26

0x42f4e0 CSEL	W8, W8, W26, #3

0x42f4e4 ADD	W10, W8, #1

0x42f4e8 CMP	W9, W10

0x42f4ec CCMP	W20, #1, #8, #3

0x42f4f0 B.GE	42f524

(572) 0x42f4f4 ORR	W1, WZR, W19

(572) 0x42f4f8 ADRP	X0,

(572) 0x42f4fc ADD	X0, X0, #1184

(572) 0x42f500 BL	402d80

(572) 0x42f504 LDP	X20, X19, [SP, #128]

(572) 0x42f508 LDP	X22, X21, [SP, #112]

(572) 0x42f50c LDP	X24, X23, [SP, #96]

(572) 0x42f510 LDP	X26, X25, [SP, #80]

(572) 0x42f514 LDP	X28, X27, [SP, #64]

(572) 0x42f518 LDP	X29, X30, [SP, #48]

(572) 0x42f51c ADD	SP, SP, #144

(572) 0x42f520 RET

(572) 0x42f524 ADD	W11, W24, #1

(572) 0x42f528 UBFM	X18, X20, #61, #60

(572) 0x42f52c ADD	W15, W24, #3

(572) 0x42f530 SUB	X0, X20, #1

(572) 0x42f534 ADD	W14, W9, W25

(572) 0x42f538 ORR	W10, WZR, WZR

(572) 0x42f53c PTRUE	P0.D, ALL

(572) 0x42f540 UBFM	X13, X22, #61, #60

(572) 0x42f544 SBFM	X16, X11, #61, #31

(572) 0x42f548 ADD	X1, X23, X18

(572) 0x42f54c SBFM	X17, X15, #61, #31

(572) 0x42f550 ADD	X12, X23, X16

(572) 0x42f554 STP	X12, X11, [SP, #16]

(572) 0x42f558 ADD	X16, X16, #8

(572) 0x42f55c ADD	X15, X23, X17

(572) 0x42f560 ADD	X1, X1, X17

(572) 0x42f564 SUB	X17, X16, X18

(572) 0x42f568 ADD	X3, X23, X16

(572) 0x42f56c CNTW	X16, ALL

(572) 0x42f570 CMP	X16, #20

(572) 0x42f574 ADD	X2, X23, X17

(572) 0x42f578 MOVZ	W17, #20

(572) 0x42f57c SUB	W18, W11, W0

(572) 0x42f580 CSEL	X17, X16, X17, #8

(572) 0x42f584 ANDS	XZR, X0, #6112

(572) 0x42f588 SUB	W14, W14, W20

(572) 0x42f58c ADD	W12, W14, #1

(572) 0x42f590 SUB	X0, XZR, X0,LSL #3

(572) 0x42f594 CCMP	W18, W11, #0, #0

(572) 0x42f598 ADD	X11, X15, #16

(572) 0x42f59c ORR	W5, WZR, W12

(572) 0x42f5a0 STR	X11, [SP, #8]

(572) 0x42f5a4 CNTD	X11, ALL

(572) 0x42f5a8 CSINC	W18, WZR, WZR, #13

(572) 0x42f5ac CMP	X15, X3

(572) 0x42f5b0 MOVZ	W3, #1

(572) 0x42f5b4 CCMP	X2, X1, #2, #3

(572) 0x42f5b8 ORR	W2, WZR, W12

(572) 0x42f5bc SUB	X4, X3, X11

(572) 0x42f5c0 CSINC	W1, WZR, WZR, #2

(572) 0x42f5c4 B	42f5dc

(572) 0x42f5c8 CMP	W9, W8

(572) 0x42f5cc ORR	W9, WZR, W6

(572) 0x42f5d0 ADD	W10, W10, #1

(572) 0x42f5d4 ADD	W5, W5, #1

(572) 0x42f5d8 B.EQ	42f4f4

(572) 0x42f5dc ADD	W6, W9, #1

(572) 0x42f5e0 SBFM	X25, X5, #0, #31

(572) 0x42f5e4 CMP	X17, X20

(572) 0x42f5e8 ADD	W3, W6, W21

(572) 0x42f5ec MADD	X26, X13, X25, X15

(572) 0x42f5f0 SBFM	X3, X3, #0, #31

(572) 0x42f5f4 MADD	X3, X22, X3, XZR

(572) 0x42f5f8 ADD	X7, X23, X3,LSL #3

(572) 0x42f5fc B.LS	42f608

(572) 0x42f600 ORR	X27, XZR, XZR

(572) 0x42f604 B	42f6e0

(572) 0x42f608 LDR	X12, [SP, #16]

(572) 0x42f60c ADD	W3, W2, W10

(572) 0x42f610 ORR	W14, WZR, W19

(572) 0x42f614 SBFM	X3, X3, #0, #31

(572) 0x42f618 MADD	X3, X13, X3, X12

(572) 0x42f61c ADD	X19, X3, X0

(572) 0x42f620 CMP	X19, X3

(572) 0x42f624 CSINC	W3, W18, WZR, #9

(572) 0x42f628 ORR	W3, W3, W1

(572) 0x42f62c TBZ	W3, #0, 42f640

0x42f630 ORR	X27, XZR, XZR

0x42f634 ORR	W19, WZR, W14

0x42f638 B	42f6e0

0x42f63c HINT	#0

(572) 0x42f640 UDIV	X3, X20, X16

(572) 0x42f644 CNTD	X12, ALL

(572) 0x42f648 ORR	W11, WZR, W1

(572) 0x42f64c ORR	X1, XZR, X0

(572) 0x42f650 ORR	W0, WZR, W18

(572) 0x42f654 ORR	W18, WZR, W2

(572) 0x42f658 ORR	W2, WZR, W24

(572) 0x42f65c ORR	X28, XZR, XZR

(572) 0x42f660 ADDVL	X19, X26, #1

(572) 0x42f664 UMSUBL	X30, W3, W16, X20

(572) 0x42f668 UMADDL	X27, W3, W16, XZR

(572) 0x42f66c SUB	X3, XZR, X12

(572) 0x42f670 LDR	X12, [SP, #24]

(572) 0x42f674 ORR	W24, WZR, W12

(572) 0x42f678 HINT	#0

(572) 0x42f67c HINT	#0

  (571) 0x42f680 ADD	X12, X7, W24,SXTW #3

  (571) 0x42f684 SUB	W24, W24, W16

  (571) 0x42f688 ADD	X12, X12, X4,LSL #3

  (571) 0x42f68c LD1D	{Z0.D}, P0/Z, [X12, MUL VL]

  (571) 0x42f690 LD1D	{Z1.D}, P0/Z, [X12, X3,LSL #3]

  (571) 0x42f694 REV	Z0.D, Z0.D

  (571) 0x42f698 REV	Z1.D, Z1.D

  (571) 0x42f69c FNEG	Z0.D, P0/M, Z0.D

  (571) 0x42f6a0 FNEG	Z1.D, P0/M, Z1.D

  (571) 0x42f6a4 ST1D	{Z0.D}, P0, [X26, X28,LSL #3]

  (571) 0x42f6a8 ST1D	{Z1.D}, P0, [X19, X28,LSL #3]

  (571) 0x42f6ac ADD	X28, X28, X16

  (571) 0x42f6b0 CMP	X27, X28

  (571) 0x42f6b4 B.NE	42f680

(572) 0x42f6b8 ORR	W24, WZR, W2

(572) 0x42f6bc ORR	W19, WZR, W14

(572) 0x42f6c0 ORR	W2, WZR, W18

(572) 0x42f6c4 ORR	W18, WZR, W0

(572) 0x42f6c8 ORR	X0, XZR, X1

(572) 0x42f6cc ORR	W1, WZR, W11

(572) 0x42f6d0 CBZ	X30, 42f5c8

0x42f6d4 HINT	#0

0x42f6d8 HINT	#0

0x42f6dc HINT	#0

(572) 0x42f6e0 SUB	W12, W20, W27

(572) 0x42f6e4 ORR	X28, XZR, X27

(572) 0x42f6e8 ANDS	X30, X12, #4160

(572) 0x42f6ec B.EQ	42f71c

(572) 0x42f6f0 LDR	X11, [SP, #24]

(572) 0x42f6f4 ORR	X28, XZR, X27

(572) 0x42f6f8 SUB	W3, W11, W27

(572) 0x42f6fc HINT	#0

  (574) 0x42f700 LDR	D0, [X7, X3,SXTW #3]

  (574) 0x42f704 SUB	W3, W3, #1

  (574) 0x42f708 SUBS	X30, X30, #1

  (574) 0x42f70c FNEG	D0, D0

  (574) 0x42f710 STR	D0, [X26, X28,LSL #3]

  (574) 0x42f714 ADD	X28, X28, #1

  (574) 0x42f718 B.NE	42f700

(572) 0x42f71c ORN	X12, XZR, X27

(572) 0x42f720 ADD	X12, X12, X20

(572) 0x42f724 CMP	X12, #3

(572) 0x42f728 B.CC	42f5c8

0x42f72c MADD	X12, X13, X25, XZR

0x42f730 LDR	X11, [SP, #8]

0x42f734 SUB	X25, X20, X28

0x42f738 SUB	W26, W24, W28

0x42f73c ADD	X12, X12, X28,LSL #3

0x42f740 ADD	X27, X11, X12

(573) 0x42f744 ADD	W12, W26, #1

(573) 0x42f748 SUB	X25, X25, #4

(573) 0x42f74c LDR	D0, [X7, X12,SXTW #3]

(573) 0x42f750 SUB	W12, W26, #1

(573) 0x42f754 FNEG	D0, D0

(573) 0x42f758 STUR	D0, [X27, #496]

(573) 0x42f75c LDR	D0, [X7, X26,SXTW #3]

(573) 0x42f760 FNEG	D0, D0

(573) 0x42f764 STUR	D0, [X27, #504]

(573) 0x42f768 LDR	D0, [X7, X12,SXTW #3]

(573) 0x42f76c SUB	W12, W26, #2

(573) 0x42f770 SUB	W26, W26, #4

(573) 0x42f774 FNEG	D0, D0

(573) 0x42f778 STR	D0, [X27]

(573) 0x42f77c LDR	D0, [X7, X12,SXTW #3]

(573) 0x42f780 FNEG	D0, D0

(573) 0x42f784 STR	D0, [X27, #8]

(573) 0x42f788 ADD	X27, X27, #32

(573) 0x42f78c CBNZ	X25, 42f744

0x42f790 B	42f5c8

0x42f794 HINT	#0

0x42f798 HINT	#0

0x42f79c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:418-421
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:418-421

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 7.25 to 0.94 cycles (7.73x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.25 to 0.50 cycles (14.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	58
loop length	232
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	2.50	2.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Overall L1	7.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.25 cycles. At this rate:

7% of peak load performance is reached (7.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42f450

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42f504 <.omp_outlined..70+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4644a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42f524 <.omp_outlined..70+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42f6e0 <.omp_outlined..70+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
MADD X12, X13, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X11, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42f5c8 <.omp_outlined..70+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	update_halo.cpp:418-421
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:418-421

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.25 to 0.50 cycles (14.50x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	58
loop length	232
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	2.50	2.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Overall L1	7.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.25 cycles. At this rate:

7% of peak load performance is reached (7.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42f450

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42f504 <.omp_outlined..70+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4644a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42f524 <.omp_outlined..70+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42f6e0 <.omp_outlined..70+0x290>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
MADD X12, X13, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X11, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42f5c8 <.omp_outlined..70+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..70–	0.01	0
▼Loop 572 - update_halo.cpp:418-421 - exec–	0	0
○Loop 574 - update_halo.cpp:420-421 - exec	0.01	0
○Loop 571 - update_halo.cpp:420-421 - exec	0	0
○Loop 573 - update_halo.cpp:420-421 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code