OV - exec - Function .omp

	Function: .omp_outlined..68	Module: exec	Source: update_halo.cpp:408-411	Coverage: 0.03%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 408 - 411

--------------------------------------------------------------------------------

408: #pragma omp parallel for simd

409:       for (int k = (y_min - depth + 1); k < (y_max + 1 + depth + 2); k++) {

410:         for (int j = 0; j < depth; ++j) {

411:           field.xvel1(1 - j, k) = -field.xvel1(1 + 2 + j, k);

0x42f1b0 SUB	SP, SP, #128

0x42f1b4 STP	X29, X30, [SP, #32]

0x42f1b8 STP	X28, X27, [SP, #48]

0x42f1bc STP	X26, X25, [SP, #64]

0x42f1c0 STP	X24, X23, [SP, #80]

0x42f1c4 STP	X22, X21, [SP, #96]

0x42f1c8 STP	X20, X19, [SP, #112]

0x42f1cc ADD	X29, SP, #32

0x42f1d0 LDR	W20, [X3]

0x42f1d4 LDR	W8, [X4]

0x42f1d8 LDR	W22, [X2]

0x42f1dc ADD	W8, W20, W8

0x42f1e0 SUB	W9, W22, W20

0x42f1e4 ADD	W8, W8, #1

0x42f1e8 SUBS	W24, W8, W9

0x42f1ec B.LT	42f264

0x42f1f0 LDR	W19, [X0]

0x42f1f4 LDR	X23, [X5, #192]

0x42f1f8 LDR	X21, [X5, #208]

0x42f1fc MOVZ	W8, #1

0x42f200 ADRP	X0,

0x42f204 ADD	X0, X0, #1088

0x42f208 ADD	X3, SP, #16

0x42f20c SUB	X4, X29, #4

0x42f210 STP	W24, WZR, [X29, #504]

0x42f214 SUB	X5, X29, #8

0x42f218 SUB	X6, X29, #12

0x42f21c MOVZ	W2, #34

0x42f220 STUR	W8, [X29, #500]

0x42f224 STR	WZR, [SP, #16]

0x42f228 STR	W8, [SP]

0x42f22c MOVZ	W7, #1

0x42f230 ORR	W1, WZR, W19

0x42f234 BL	402f40

0x42f238 LDP	W8, W9, [X29, #504]

0x42f23c CMP	W8, W24

0x42f240 CSEL	W8, W8, W24, #3

0x42f244 ADD	W10, W8, #1

0x42f248 CMP	W9, W10

0x42f24c CCMP	W20, #1, #8, #3

0x42f250 B.GE	42f284

(565) 0x42f254 ORR	W1, WZR, W19

(565) 0x42f258 ADRP	X0,

(565) 0x42f25c ADD	X0, X0, #1112

(565) 0x42f260 BL	402d80

(565) 0x42f264 LDP	X20, X19, [SP, #112]

(565) 0x42f268 LDP	X22, X21, [SP, #96]

(565) 0x42f26c LDP	X24, X23, [SP, #80]

(565) 0x42f270 LDP	X26, X25, [SP, #64]

(565) 0x42f274 LDP	X28, X27, [SP, #48]

(565) 0x42f278 LDP	X29, X30, [SP, #32]

(565) 0x42f27c ADD	SP, SP, #128

(565) 0x42f280 RET

(565) 0x42f284 ADD	X15, X21, #24

(565) 0x42f288 UBFM	X16, X20, #61, #60

(565) 0x42f28c ADD	W14, W9, W22

(565) 0x42f290 ADD	X6, X21, #16

(565) 0x42f294 MOVZ	W0, #12

(565) 0x42f298 RDVL	X5, #1

(565) 0x42f29c SUB	X11, X20, #1

(565) 0x42f2a0 ORR	W10, WZR, WZR

(565) 0x42f2a4 RDVL	X18, #2

(565) 0x42f2a8 RDVL	X1, #62

(565) 0x42f2ac ADD	X2, X15, X16

(565) 0x42f2b0 ADD	X12, X21, #8

(565) 0x42f2b4 UBFM	X13, X23, #61, #60

(565) 0x42f2b8 SUB	X16, X21, X16

(565) 0x42f2bc SUB	X17, XZR, X11,LSL #3

(565) 0x42f2c0 ADD	X3, X16, #16

(565) 0x42f2c4 CNTW	X16, ALL

(565) 0x42f2c8 CMP	X16, #12

(565) 0x42f2cc SUB	W14, W14, W20

(565) 0x42f2d0 ADD	W14, W14, #1

(565) 0x42f2d4 ADDVL	X4, X15, #1

(565) 0x42f2d8 SUB	X5, X6, X5

(565) 0x42f2dc CSEL	X0, X16, X0, #8

(565) 0x42f2e0 CMP	X15, X6

(565) 0x42f2e4 ADDVL	X6, X6, #62

(565) 0x42f2e8 CCMP	X3, X2, #2, #3

(565) 0x42f2ec PTRUE	P0.B, ALL

(565) 0x42f2f0 PTRUE	P1.D, ALL

(565) 0x42f2f4 ADD	X3, X21, #48

(565) 0x42f2f8 CSINC	W2, WZR, WZR, #2

(565) 0x42f2fc ORR	W7, WZR, W14

(565) 0x42f300 B	42f318

(565) 0x42f304 CMP	W9, W8

(565) 0x42f308 ADD	W9, W9, #1

(565) 0x42f30c ADD	W10, W10, #1

(565) 0x42f310 ADD	W7, W7, #1

(565) 0x42f314 B.EQ	42f254

(565) 0x42f318 SBFM	X22, X7, #0, #31

(565) 0x42f31c CMP	X0, X20

(565) 0x42f320 MADD	X22, X13, X22, XZR

(565) 0x42f324 B.HI	42f348

(565) 0x42f328 ADD	W23, W14, W10

(565) 0x42f32c ANDS	XZR, X11, #4227

(565) 0x42f330 SBFM	X23, X23, #0, #31

(565) 0x42f334 MADD	X23, X13, X23, X12

(565) 0x42f338 ADD	X24, X23, X17

(565) 0x42f33c CCMP	X24, X23, #2, #0

(565) 0x42f340 CSINC	W23, W2, WZR, #9

(565) 0x42f344 TBZ	W23, #0, 42f3ec

(565) 0x42f348 ORR	X23, XZR, XZR

(565) 0x42f34c SUB	W24, W20, W23

(565) 0x42f350 ANDS	X25, X24, #4160

(565) 0x42f354 ORR	X24, XZR, X23

(565) 0x42f358 B.EQ	42f384

(565) 0x42f35c SUB	X24, X22, X23,LSL #3

(565) 0x42f360 ADD	X26, X15, X22

(565) 0x42f364 ADD	X27, X12, X24

(565) 0x42f368 ORR	X24, XZR, X23

  (567) 0x42f36c LDR	D0, [X26, X24,LSL #3]

  (567) 0x42f370 ADD	X24, X24, #1

  (567) 0x42f374 SUBS	X25, X25, #1

  (567) 0x42f378 FNEG	D0, D0

  (567) 0x42f37c STR	D0, [X27], #504

  (567) 0x42f380 B.NE	42f36c

(565) 0x42f384 ORN	X23, XZR, X23

(565) 0x42f388 ADD	X23, X23, X20

(565) 0x42f38c CMP	X23, #3

(565) 0x42f390 B.CC	42f304

(565) 0x42f394 UBFM	X25, X24, #61, #60

(565) 0x42f398 SUB	X24, X20, X24

(565) 0x42f39c ADD	X23, X22, X25

(565) 0x42f3a0 SUB	X22, X22, X25

(565) 0x42f3a4 ADD	X23, X3, X23

(565) 0x42f3a8 ADD	X22, X21, X22

  (566) 0x42f3ac LDUR	D0, [X23, #488]

  (566) 0x42f3b0 SUBS	X24, X24, #4

  (566) 0x42f3b4 FNEG	D0, D0

  (566) 0x42f3b8 STR	D0, [X22, #8]

  (566) 0x42f3bc LDUR	D0, [X23, #496]

  (566) 0x42f3c0 FNEG	D0, D0

  (566) 0x42f3c4 STR	D0, [X22]

  (566) 0x42f3c8 LDUR	D0, [X23, #504]

  (566) 0x42f3cc FNEG	D0, D0

  (566) 0x42f3d0 STUR	D0, [X22, #504]

  (566) 0x42f3d4 LDR	D0, [X23], #32

  (566) 0x42f3d8 FNEG	D0, D0

  (566) 0x42f3dc STUR	D0, [X22, #496]

  (566) 0x42f3e0 SUB	X22, X22, #32

  (566) 0x42f3e4 B.NE	42f3ac

(565) 0x42f3e8 B	42f304

(565) 0x42f3ec UDIV	X23, X20, X16

(565) 0x42f3f0 ORR	X26, XZR, X6

(565) 0x42f3f4 ORR	X27, XZR, X5

(565) 0x42f3f8 ORR	X28, XZR, X4

(565) 0x42f3fc ORR	X30, XZR, X15

(565) 0x42f400 UMSUBL	X24, W23, W16, X20

(565) 0x42f404 UMADDL	X23, W23, W16, XZR

(565) 0x42f408 ORR	X25, XZR, X23

  (568) 0x42f40c LD1B	{Z0.B}, P0/Z, [X30, X22]

  (568) 0x42f410 LD1B	{Z1.B}, P0/Z, [X28, X22]

  (568) 0x42f414 ADD	X30, X30, X18

  (568) 0x42f418 ADD	X28, X28, X18

  (568) 0x42f41c SUBS	X25, X25, X16

  (568) 0x42f420 FNEG	Z0.D, P1/M, Z0.D

  (568) 0x42f424 FNEG	Z1.D, P1/M, Z1.D

  (568) 0x42f428 REV	Z0.D, Z0.D

  (568) 0x42f42c ST1B	{Z0.B}, P0, [X27, X22]

  (568) 0x42f430 REV	Z0.D, Z1.D

  (568) 0x42f434 ADD	X27, X27, X1

  (568) 0x42f438 ST1B	{Z0.B}, P0, [X26, X22]

  (568) 0x42f43c ADD	X26, X26, X1

  (568) 0x42f440 B.NE	42f40c

(565) 0x42f444 CBNZ	X24, 42f34c

0x42f448 B	42f304

0x42f44c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:408-411
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:408-411.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.67 to 0.72 cycles (7.88x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	43
loop length	172
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.25
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42f1b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42f264 <.omp_outlined..68+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464200>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1088	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42f284 <.omp_outlined..68+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 42f304 <.omp_outlined..68+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	update_halo.cpp:408-411
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:408-411.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	43
loop length	172
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.25
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42f1b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42f264 <.omp_outlined..68+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464200>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1088	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42f284 <.omp_outlined..68+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 42f304 <.omp_outlined..68+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..68–	0.03	0.01
▼Loop 565 - update_halo.cpp:408-411 - exec–	0	0
○Loop 567 - update_halo.cpp:410-411 - exec	0.03	0.01
○Loop 568 - update_halo.cpp:410-411 - exec	0	0
○Loop 566 - update_halo.cpp:410-411 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code