OV - exec - Function .omp

	Function: .omp_outlined..60	Module: exec	Source: update_halo.cpp:365-368	Coverage: 0.03%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 365 - 368

--------------------------------------------------------------------------------

365: #pragma omp parallel for simd

366:       for (int k = (y_min - depth + 1); k < (y_max + 1 + depth + 2); k++) {

367:         for (int j = 0; j < depth; ++j) {

368:           field.xvel0(1 - j, k) = -field.xvel0(1 + 2 + j, k);

0x42e810 SUB	SP, SP, #128

0x42e814 STP	X29, X30, [SP, #32]

0x42e818 STP	X28, X27, [SP, #48]

0x42e81c STP	X26, X25, [SP, #64]

0x42e820 STP	X24, X23, [SP, #80]

0x42e824 STP	X22, X21, [SP, #96]

0x42e828 STP	X20, X19, [SP, #112]

0x42e82c ADD	X29, SP, #32

0x42e830 LDR	W20, [X3]

0x42e834 LDR	W8, [X4]

0x42e838 LDR	W22, [X2]

0x42e83c ADD	W8, W20, W8

0x42e840 SUB	W9, W22, W20

0x42e844 ADD	W8, W8, #1

0x42e848 SUBS	W24, W8, W9

0x42e84c B.LT	42e8c4

0x42e850 LDR	W19, [X0]

0x42e854 LDR	X23, [X5, #168]

0x42e858 LDR	X21, [X5, #184]

0x42e85c MOVZ	W8, #1

0x42e860 ADRP	X0,

0x42e864 ADD	X0, X0, #800

0x42e868 ADD	X3, SP, #16

0x42e86c SUB	X4, X29, #4

0x42e870 STP	W24, WZR, [X29, #504]

0x42e874 SUB	X5, X29, #8

0x42e878 SUB	X6, X29, #12

0x42e87c MOVZ	W2, #34

0x42e880 STUR	W8, [X29, #500]

0x42e884 STR	WZR, [SP, #16]

0x42e888 STR	W8, [SP]

0x42e88c MOVZ	W7, #1

0x42e890 ORR	W1, WZR, W19

0x42e894 BL	402f40

0x42e898 LDP	W8, W9, [X29, #504]

0x42e89c CMP	W8, W24

0x42e8a0 CSEL	W8, W8, W24, #3

0x42e8a4 ADD	W10, W8, #1

0x42e8a8 CMP	W9, W10

0x42e8ac CCMP	W20, #1, #8, #3

0x42e8b0 B.GE	42e8e4

(543) 0x42e8b4 ORR	W1, WZR, W19

(543) 0x42e8b8 ADRP	X0,

(543) 0x42e8bc ADD	X0, X0, #824

(543) 0x42e8c0 BL	402d80

(543) 0x42e8c4 LDP	X20, X19, [SP, #112]

(543) 0x42e8c8 LDP	X22, X21, [SP, #96]

(543) 0x42e8cc LDP	X24, X23, [SP, #80]

(543) 0x42e8d0 LDP	X26, X25, [SP, #64]

(543) 0x42e8d4 LDP	X28, X27, [SP, #48]

(543) 0x42e8d8 LDP	X29, X30, [SP, #32]

(543) 0x42e8dc ADD	SP, SP, #128

(543) 0x42e8e0 RET

(543) 0x42e8e4 ADD	X15, X21, #24

(543) 0x42e8e8 UBFM	X16, X20, #61, #60

(543) 0x42e8ec ADD	W14, W9, W22

(543) 0x42e8f0 ADD	X6, X21, #16

(543) 0x42e8f4 MOVZ	W0, #12

(543) 0x42e8f8 RDVL	X5, #1

(543) 0x42e8fc SUB	X11, X20, #1

(543) 0x42e900 ORR	W10, WZR, WZR

(543) 0x42e904 RDVL	X18, #2

(543) 0x42e908 RDVL	X1, #62

(543) 0x42e90c ADD	X2, X15, X16

(543) 0x42e910 ADD	X12, X21, #8

(543) 0x42e914 UBFM	X13, X23, #61, #60

(543) 0x42e918 SUB	X16, X21, X16

(543) 0x42e91c SUB	X17, XZR, X11,LSL #3

(543) 0x42e920 ADD	X3, X16, #16

(543) 0x42e924 CNTW	X16, ALL

(543) 0x42e928 CMP	X16, #12

(543) 0x42e92c SUB	W14, W14, W20

(543) 0x42e930 ADD	W14, W14, #1

(543) 0x42e934 ADDVL	X4, X15, #1

(543) 0x42e938 SUB	X5, X6, X5

(543) 0x42e93c CSEL	X0, X16, X0, #8

(543) 0x42e940 CMP	X15, X6

(543) 0x42e944 ADDVL	X6, X6, #62

(543) 0x42e948 CCMP	X3, X2, #2, #3

(543) 0x42e94c PTRUE	P0.B, ALL

(543) 0x42e950 PTRUE	P1.D, ALL

(543) 0x42e954 ADD	X3, X21, #48

(543) 0x42e958 CSINC	W2, WZR, WZR, #2

(543) 0x42e95c ORR	W7, WZR, W14

(543) 0x42e960 B	42e978

(543) 0x42e964 CMP	W9, W8

(543) 0x42e968 ADD	W9, W9, #1

(543) 0x42e96c ADD	W10, W10, #1

(543) 0x42e970 ADD	W7, W7, #1

(543) 0x42e974 B.EQ	42e8b4

(543) 0x42e978 SBFM	X22, X7, #0, #31

(543) 0x42e97c CMP	X0, X20

(543) 0x42e980 MADD	X22, X13, X22, XZR

(543) 0x42e984 B.HI	42e9a8

(543) 0x42e988 ADD	W23, W14, W10

(543) 0x42e98c ANDS	XZR, X11, #4227

(543) 0x42e990 SBFM	X23, X23, #0, #31

(543) 0x42e994 MADD	X23, X13, X23, X12

(543) 0x42e998 ADD	X24, X23, X17

(543) 0x42e99c CCMP	X24, X23, #2, #0

(543) 0x42e9a0 CSINC	W23, W2, WZR, #9

(543) 0x42e9a4 TBZ	W23, #0, 42ea4c

(543) 0x42e9a8 ORR	X23, XZR, XZR

(543) 0x42e9ac SUB	W24, W20, W23

(543) 0x42e9b0 ANDS	X25, X24, #4160

(543) 0x42e9b4 ORR	X24, XZR, X23

(543) 0x42e9b8 B.EQ	42e9e4

(543) 0x42e9bc SUB	X24, X22, X23,LSL #3

(543) 0x42e9c0 ADD	X26, X15, X22

(543) 0x42e9c4 ADD	X27, X12, X24

(543) 0x42e9c8 ORR	X24, XZR, X23

  (545) 0x42e9cc LDR	D0, [X26, X24,LSL #3]

  (545) 0x42e9d0 ADD	X24, X24, #1

  (545) 0x42e9d4 SUBS	X25, X25, #1

  (545) 0x42e9d8 FNEG	D0, D0

  (545) 0x42e9dc STR	D0, [X27], #504

  (545) 0x42e9e0 B.NE	42e9cc

(543) 0x42e9e4 ORN	X23, XZR, X23

(543) 0x42e9e8 ADD	X23, X23, X20

(543) 0x42e9ec CMP	X23, #3

(543) 0x42e9f0 B.CC	42e964

(543) 0x42e9f4 UBFM	X25, X24, #61, #60

(543) 0x42e9f8 SUB	X24, X20, X24

(543) 0x42e9fc ADD	X23, X22, X25

(543) 0x42ea00 SUB	X22, X22, X25

(543) 0x42ea04 ADD	X23, X3, X23

(543) 0x42ea08 ADD	X22, X21, X22

  (544) 0x42ea0c LDUR	D0, [X23, #488]

  (544) 0x42ea10 SUBS	X24, X24, #4

  (544) 0x42ea14 FNEG	D0, D0

  (544) 0x42ea18 STR	D0, [X22, #8]

  (544) 0x42ea1c LDUR	D0, [X23, #496]

  (544) 0x42ea20 FNEG	D0, D0

  (544) 0x42ea24 STR	D0, [X22]

  (544) 0x42ea28 LDUR	D0, [X23, #504]

  (544) 0x42ea2c FNEG	D0, D0

  (544) 0x42ea30 STUR	D0, [X22, #504]

  (544) 0x42ea34 LDR	D0, [X23], #32

  (544) 0x42ea38 FNEG	D0, D0

  (544) 0x42ea3c STUR	D0, [X22, #496]

  (544) 0x42ea40 SUB	X22, X22, #32

  (544) 0x42ea44 B.NE	42ea0c

(543) 0x42ea48 B	42e964

(543) 0x42ea4c UDIV	X23, X20, X16

(543) 0x42ea50 ORR	X26, XZR, X6

(543) 0x42ea54 ORR	X27, XZR, X5

(543) 0x42ea58 ORR	X28, XZR, X4

(543) 0x42ea5c ORR	X30, XZR, X15

(543) 0x42ea60 UMSUBL	X24, W23, W16, X20

(543) 0x42ea64 UMADDL	X23, W23, W16, XZR

(543) 0x42ea68 ORR	X25, XZR, X23

  (546) 0x42ea6c LD1B	{Z0.B}, P0/Z, [X30, X22]

  (546) 0x42ea70 LD1B	{Z1.B}, P0/Z, [X28, X22]

  (546) 0x42ea74 ADD	X30, X30, X18

  (546) 0x42ea78 ADD	X28, X28, X18

  (546) 0x42ea7c SUBS	X25, X25, X16

  (546) 0x42ea80 FNEG	Z0.D, P1/M, Z0.D

  (546) 0x42ea84 FNEG	Z1.D, P1/M, Z1.D

  (546) 0x42ea88 REV	Z0.D, Z0.D

  (546) 0x42ea8c ST1B	{Z0.B}, P0, [X27, X22]

  (546) 0x42ea90 REV	Z0.D, Z1.D

  (546) 0x42ea94 ADD	X27, X27, X1

  (546) 0x42ea98 ST1B	{Z0.B}, P0, [X26, X22]

  (546) 0x42ea9c ADD	X26, X26, X1

  (546) 0x42eaa0 B.NE	42ea6c

(543) 0x42eaa4 CBNZ	X24, 42e9ac

0x42eaa8 B	42e964

0x42eaac HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:365-368
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:365-368.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.67 to 0.72 cycles (7.88x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	43
loop length	172
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.25
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42e810

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42e8c4 <.omp_outlined..60+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464860>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #800	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42e8e4 <.omp_outlined..60+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 42e964 <.omp_outlined..60+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	update_halo.cpp:365-368
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:365-368.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	43
loop length	172
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.50	5.50	5.50	5.50	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.25
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42e810

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W8, W20, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42e8c4 <.omp_outlined..60+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <464860>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #800	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42e8e4 <.omp_outlined..60+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 42e964 <.omp_outlined..60+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..60–	0.03	0.01
▼Loop 543 - update_halo.cpp:365-368 - exec–	0	0
○Loop 545 - update_halo.cpp:367-368 - exec	0.03	0.01
○Loop 546 - update_halo.cpp:367-368 - exec	0	0
○Loop 544 - update_halo.cpp:367-368 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code