OV - exec - Function .omp

	Function: .omp_outlined..46	Module: exec	Source: update_halo.cpp:289-292 [...]	Coverage: 0.01%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 289 - 292

--------------------------------------------------------------------------------

289: #pragma omp parallel for simd

290:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

291:         for (int j = 0; j < depth; ++j) {

292:           field.viscosity(x_max + 2 + j, k) = field.viscosity(x_max + 1 - j, k);

0x42d7e0 SUB	SP, SP, #144

0x42d7e4 STP	X29, X30, [SP, #48]

0x42d7e8 STP	X28, X27, [SP, #64]

0x42d7ec STP	X26, X25, [SP, #80]

0x42d7f0 STP	X24, X23, [SP, #96]

0x42d7f4 STP	X22, X21, [SP, #112]

0x42d7f8 STP	X20, X19, [SP, #128]

0x42d7fc ADD	X29, SP, #48

0x42d800 LDR	W25, [X2]

0x42d804 LDR	W20, [X3]

0x42d808 LDR	W8, [X4]

0x42d80c SUB	W21, W25, W20

0x42d810 ADD	W8, W8, W20

0x42d814 SUBS	W26, W8, W21

0x42d818 B.LT	42d890

0x42d81c LDR	W19, [X0]

0x42d820 LDR	X22, [X5, #120]

0x42d824 LDR	X23, [X5, #136]

0x42d828 MOVZ	W8, #1

0x42d82c ADRP	X0,

0x42d830 ADD	X0, X0, #296

0x42d834 SUB	X3, X29, #16

0x42d838 SUB	X4, X29, #4

0x42d83c LDR	W24, [X6]

0x42d840 SUB	X5, X29, #8

0x42d844 SUB	X6, X29, #12

0x42d848 MOVZ	W2, #34

0x42d84c STP	W26, WZR, [X29, #504]

0x42d850 STP	WZR, W8, [X29, #496]

0x42d854 STR	W8, [SP]

0x42d858 MOVZ	W7, #1

0x42d85c ORR	W1, WZR, W19

0x42d860 BL	402f40

0x42d864 LDP	W8, W9, [X29, #504]

0x42d868 CMP	W8, W26

0x42d86c CSEL	W8, W8, W26, #3

0x42d870 ADD	W10, W8, #1

0x42d874 CMP	W9, W10

0x42d878 CCMP	W20, #1, #8, #3

0x42d87c B.GE	42d8b0

(494) 0x42d880 ORR	W1, WZR, W19

(494) 0x42d884 ADRP	X0,

(494) 0x42d888 ADD	X0, X0, #320

(494) 0x42d88c BL	402d80

(494) 0x42d890 LDP	X20, X19, [SP, #128]

(494) 0x42d894 LDP	X22, X21, [SP, #112]

(494) 0x42d898 LDP	X24, X23, [SP, #96]

(494) 0x42d89c LDP	X26, X25, [SP, #80]

(494) 0x42d8a0 LDP	X28, X27, [SP, #64]

(494) 0x42d8a4 LDP	X29, X30, [SP, #48]

(494) 0x42d8a8 ADD	SP, SP, #144

(494) 0x42d8ac RET

(494) 0x42d8b0 ADD	W11, W24, #1

(494) 0x42d8b4 UBFM	X18, X20, #61, #60

(494) 0x42d8b8 ADD	W15, W24, #2

(494) 0x42d8bc SUB	X0, X20, #1

(494) 0x42d8c0 ADD	W14, W9, W25

(494) 0x42d8c4 ORR	W10, WZR, WZR

(494) 0x42d8c8 PTRUE	P0.D, ALL

(494) 0x42d8cc UBFM	X13, X22, #61, #60

(494) 0x42d8d0 SBFM	X16, X11, #61, #31

(494) 0x42d8d4 ADD	X1, X23, X18

(494) 0x42d8d8 SBFM	X17, X15, #61, #31

(494) 0x42d8dc ADD	X12, X23, X16

(494) 0x42d8e0 STP	X12, X11, [SP, #16]

(494) 0x42d8e4 ADD	X16, X16, #8

(494) 0x42d8e8 ADD	X15, X23, X17

(494) 0x42d8ec ADD	X1, X1, X17

(494) 0x42d8f0 SUB	X17, X16, X18

(494) 0x42d8f4 ADD	X3, X23, X16

(494) 0x42d8f8 CNTW	X16, ALL

(494) 0x42d8fc CMP	X16, #28

(494) 0x42d900 ADD	X2, X23, X17

(494) 0x42d904 MOVZ	W17, #28

(494) 0x42d908 SUB	W18, W11, W0

(494) 0x42d90c CSEL	X17, X16, X17, #8

(494) 0x42d910 ANDS	XZR, X0, #6112

(494) 0x42d914 SUB	W14, W14, W20

(494) 0x42d918 ADD	W12, W14, #1

(494) 0x42d91c SUB	X0, XZR, X0,LSL #3

(494) 0x42d920 CCMP	W18, W11, #0, #0

(494) 0x42d924 ADD	X11, X15, #16

(494) 0x42d928 ORR	W5, WZR, W12

(494) 0x42d92c STR	X11, [SP, #8]

(494) 0x42d930 CNTD	X11, ALL

(494) 0x42d934 CSINC	W18, WZR, WZR, #13

(494) 0x42d938 CMP	X15, X3

(494) 0x42d93c MOVZ	W3, #1

(494) 0x42d940 CCMP	X2, X1, #2, #3

(494) 0x42d944 ORR	W2, WZR, W12

(494) 0x42d948 SUB	X4, X3, X11

(494) 0x42d94c CSINC	W1, WZR, WZR, #2

(494) 0x42d950 B	42d974

0x42d954 HINT	#0

0x42d958 HINT	#0

0x42d95c HINT	#0

(494) 0x42d960 CMP	W9, W8

(494) 0x42d964 ORR	W9, WZR, W6

(494) 0x42d968 ADD	W10, W10, #1

(494) 0x42d96c ADD	W5, W5, #1

(494) 0x42d970 B.EQ	42d880

(494) 0x42d974 ADD	W6, W9, #1

(494) 0x42d978 SBFM	X25, X5, #0, #31

(494) 0x42d97c CMP	X17, X20

(494) 0x42d980 ADD	W3, W6, W21

(494) 0x42d984 MADD	X26, X13, X25, X15

(494) 0x42d988 SBFM	X3, X3, #0, #31

(494) 0x42d98c MADD	X3, X22, X3, XZR

(494) 0x42d990 ADD	X7, X23, X3,LSL #3

(494) 0x42d994 B.LS	42d9a0

(494) 0x42d998 ORR	X27, XZR, XZR

(494) 0x42d99c B	42da6c

(494) 0x42d9a0 LDR	X12, [SP, #16]

(494) 0x42d9a4 ADD	W3, W2, W10

(494) 0x42d9a8 ORR	W14, WZR, W19

(494) 0x42d9ac SBFM	X3, X3, #0, #31

(494) 0x42d9b0 MADD	X3, X13, X3, X12

(494) 0x42d9b4 ADD	X19, X3, X0

(494) 0x42d9b8 CMP	X19, X3

(494) 0x42d9bc CSINC	W3, W18, WZR, #9

(494) 0x42d9c0 ORR	W3, W3, W1

(494) 0x42d9c4 TBZ	W3, #0, 42d9e0

0x42d9c8 ORR	X27, XZR, XZR

0x42d9cc ORR	W19, WZR, W14

0x42d9d0 B	42da6c

0x42d9d4 HINT	#0

0x42d9d8 HINT	#0

0x42d9dc HINT	#0

(494) 0x42d9e0 UDIV	X3, X20, X16

(494) 0x42d9e4 CNTD	X12, ALL

(494) 0x42d9e8 ORR	W11, WZR, W1

(494) 0x42d9ec ORR	X1, XZR, X0

(494) 0x42d9f0 ORR	W0, WZR, W18

(494) 0x42d9f4 ORR	W18, WZR, W2

(494) 0x42d9f8 ORR	W2, WZR, W24

(494) 0x42d9fc ORR	X28, XZR, XZR

(494) 0x42da00 ADDVL	X19, X26, #1

(494) 0x42da04 UMSUBL	X30, W3, W16, X20

(494) 0x42da08 UMADDL	X27, W3, W16, XZR

(494) 0x42da0c SUB	X3, XZR, X12

(494) 0x42da10 LDR	X12, [SP, #24]

(494) 0x42da14 ORR	W24, WZR, W12

(494) 0x42da18 HINT	#0

(494) 0x42da1c HINT	#0

  (493) 0x42da20 ADD	X12, X7, W24,SXTW #3

  (493) 0x42da24 SUB	W24, W24, W16

  (493) 0x42da28 ADD	X12, X12, X4,LSL #3

  (493) 0x42da2c LD1D	{Z0.D}, P0/Z, [X12, MUL VL]

  (493) 0x42da30 LD1D	{Z1.D}, P0/Z, [X12, X3,LSL #3]

  (493) 0x42da34 REV	Z0.D, Z0.D

  (493) 0x42da38 REV	Z1.D, Z1.D

  (493) 0x42da3c ST1D	{Z0.D}, P0, [X26, X28,LSL #3]

  (493) 0x42da40 ST1D	{Z1.D}, P0, [X19, X28,LSL #3]

  (493) 0x42da44 ADD	X28, X28, X16

  (493) 0x42da48 CMP	X27, X28

  (493) 0x42da4c B.NE	42da20

(494) 0x42da50 ORR	W24, WZR, W2

(494) 0x42da54 ORR	W19, WZR, W14

(494) 0x42da58 ORR	W2, WZR, W18

(494) 0x42da5c ORR	W18, WZR, W0

(494) 0x42da60 ORR	X0, XZR, X1

(494) 0x42da64 ORR	W1, WZR, W11

(494) 0x42da68 CBZ	X30, 42d960

(494) 0x42da6c SUB	W12, W20, W27

(494) 0x42da70 ORR	X28, XZR, X27

(494) 0x42da74 ANDS	X30, X12, #4160

(494) 0x42da78 B.EQ	42daa0

(494) 0x42da7c LDR	X12, [SP, #24]

(494) 0x42da80 ORR	X28, XZR, X27

(494) 0x42da84 SUB	W3, W12, W27

  (496) 0x42da88 LDR	D0, [X7, X3,SXTW #3]

  (496) 0x42da8c SUB	W3, W3, #1

  (496) 0x42da90 SUBS	X30, X30, #1

  (496) 0x42da94 STR	D0, [X26, X28,LSL #3]

  (496) 0x42da98 ADD	X28, X28, #1

  (496) 0x42da9c B.NE	42da88

(494) 0x42daa0 ORN	X12, XZR, X27

(494) 0x42daa4 ADD	X12, X12, X20

(494) 0x42daa8 CMP	X12, #3

(494) 0x42daac B.CC	42d960

0x42dab0 MADD	X12, X13, X25, XZR

0x42dab4 LDR	X14, [SP, #8]

0x42dab8 SUB	X25, X20, X28

0x42dabc SUB	W26, W24, W28

0x42dac0 ADD	X12, X12, X28,LSL #3

0x42dac4 ADD	X27, X14, X12

(495) 0x42dac8 ADD	W12, W26, #1

(495) 0x42dacc SUB	X25, X25, #4

(495) 0x42dad0 LDR	D0, [X7, X12,SXTW #3]

(495) 0x42dad4 SUB	W12, W26, #1

(495) 0x42dad8 STUR	D0, [X27, #496]

(495) 0x42dadc LDR	D0, [X7, X26,SXTW #3]

(495) 0x42dae0 STUR	D0, [X27, #504]

(495) 0x42dae4 LDR	D0, [X7, X12,SXTW #3]

(495) 0x42dae8 SUB	W12, W26, #2

(495) 0x42daec SUB	W26, W26, #4

(495) 0x42daf0 STR	D0, [X27]

(495) 0x42daf4 LDR	D0, [X7, X12,SXTW #3]

(495) 0x42daf8 STR	D0, [X27, #8]

(495) 0x42dafc ADD	X27, X27, #32

(495) 0x42db00 CBNZ	X25, 42dac8

0x42db04 B	42d960

0x42db08 HINT	#0

0x42db0c HINT	#0

0x4382ac HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:289-292
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:289-292

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 7.00 to 0.91 cycles (7.72x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

7% of peak load performance is reached (7.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
34% of peak store performance is reached (16.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42d7e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42d890 <.omp_outlined..46+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <46482c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #296	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42d8b0 <.omp_outlined..46+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42da6c <.omp_outlined..46+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
MADD X12, X13, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42d960 <.omp_outlined..46+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	update_halo.cpp:289-292
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:289-292

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.00 to 0.50 cycles (14.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50
cycles	2.50	2.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	6.17	5.83	6.00	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	7.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

7% of peak load performance is reached (7.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
34% of peak store performance is reached (16.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42d7e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W21, W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W26, W8, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42d890 <.omp_outlined..46+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X5, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <46482c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #296	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W26, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP WZR, W8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W26, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42d8b0 <.omp_outlined..46+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W19, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42da6c <.omp_outlined..46+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
MADD X12, X13, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X14, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X20, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W24, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42d960 <.omp_outlined..46+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..46–	0.01	0
▼Loop 494 - update_halo.cpp:289-292 - exec–	0	0
○Loop 496 - update_halo.cpp:291-292 - exec	0.01	0
○Loop 493 - update_halo.cpp:291-292 - exec	0	0
○Loop 495 - update_halo.cpp:291-292 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code