OV - exec - Function .omp

	Function: .omp_outlined..36	Module: exec	Source: update_halo.cpp:236-239	Coverage: 0.01%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 236 - 239

--------------------------------------------------------------------------------

236: #pragma omp parallel for simd

237:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

238:         for (int j = 0; j < depth; ++j) {

239:           field.pressure(1 - j, k) = field.pressure(2 + j, k);

0x42cc10 SUB	SP, SP, #128

0x42cc14 STP	X29, X30, [SP, #32]

0x42cc18 STP	X28, X27, [SP, #48]

0x42cc1c STP	X26, X25, [SP, #64]

0x42cc20 STP	X24, X23, [SP, #80]

0x42cc24 STP	X22, X21, [SP, #96]

0x42cc28 STP	X20, X19, [SP, #112]

0x42cc2c ADD	X29, SP, #32

0x42cc30 LDR	W22, [X2]

0x42cc34 LDR	W20, [X3]

0x42cc38 LDR	W8, [X4]

0x42cc3c SUB	W9, W22, W20

0x42cc40 ADD	W8, W8, W20

0x42cc44 SUBS	W24, W8, W9

0x42cc48 B.LT	42ccc0

0x42cc4c LDR	W19, [X0]

0x42cc50 LDR	X23, [X5, #96]

0x42cc54 LDR	X21, [X5, #112]

0x42cc58 MOVZ	W8, #1

0x42cc5c ADRP	X0,

0x42cc60 ADD	X0, X0, #4032

0x42cc64 ADD	X3, SP, #16

0x42cc68 SUB	X4, X29, #4

0x42cc6c STP	W24, WZR, [X29, #504]

0x42cc70 SUB	X5, X29, #8

0x42cc74 SUB	X6, X29, #12

0x42cc78 MOVZ	W2, #34

0x42cc7c STUR	W8, [X29, #500]

0x42cc80 STR	WZR, [SP, #16]

0x42cc84 STR	W8, [SP]

0x42cc88 MOVZ	W7, #1

0x42cc8c ORR	W1, WZR, W19

0x42cc90 BL	402f40

0x42cc94 LDP	W8, W9, [X29, #504]

0x42cc98 CMP	W8, W24

0x42cc9c CSEL	W8, W8, W24, #3

0x42cca0 ADD	W10, W8, #1

0x42cca4 CMP	W9, W10

0x42cca8 CCMP	W20, #1, #8, #3

0x42ccac B.GE	42cce0

(455) 0x42ccb0 ORR	W1, WZR, W19

(455) 0x42ccb4 ADRP	X0,

(455) 0x42ccb8 ADD	X0, X0, #4056

(455) 0x42ccbc BL	402d80

(455) 0x42ccc0 LDP	X20, X19, [SP, #112]

(455) 0x42ccc4 LDP	X22, X21, [SP, #96]

(455) 0x42ccc8 LDP	X24, X23, [SP, #80]

(455) 0x42cccc LDP	X26, X25, [SP, #64]

(455) 0x42ccd0 LDP	X28, X27, [SP, #48]

(455) 0x42ccd4 LDP	X29, X30, [SP, #32]

(455) 0x42ccd8 ADD	SP, SP, #128

(455) 0x42ccdc RET

(455) 0x42cce0 ADD	W15, W9, W22

(455) 0x42cce4 CNTW	X11, ALL

(455) 0x42cce8 SUB	X2, X20, #1

(455) 0x42ccec ADD	X14, X21, #16

(455) 0x42ccf0 MOVZ	W17, #12

(455) 0x42ccf4 RDVL	X4, #1

(455) 0x42ccf8 ORR	W10, WZR, WZR

(455) 0x42ccfc ADD	X12, X21, #8

(455) 0x42cd00 UBFM	X13, X23, #61, #60

(455) 0x42cd04 RDVL	X18, #2

(455) 0x42cd08 RDVL	X0, #62

(455) 0x42cd0c ADD	X1, X21, #24

(455) 0x42cd10 CMP	X11, #12

(455) 0x42cd14 SUB	W16, W15, W20

(455) 0x42cd18 SUB	X15, XZR, X2,LSL #3

(455) 0x42cd1c UBFM	X2, X2, #61, #63

(455) 0x42cd20 CSEL	X17, X11, X17, #8

(455) 0x42cd24 ADDVL	X3, X14, #1

(455) 0x42cd28 SUB	X4, X14, X4

(455) 0x42cd2c ADD	W16, W16, #1

(455) 0x42cd30 ADDVL	X5, X14, #62

(455) 0x42cd34 PTRUE	P0.B, ALL

(455) 0x42cd38 ORR	W6, WZR, W16

(455) 0x42cd3c B	42cd54

(455) 0x42cd40 CMP	W9, W8

(455) 0x42cd44 ADD	W9, W9, #1

(455) 0x42cd48 ADD	W10, W10, #1

(455) 0x42cd4c ADD	W6, W6, #1

(455) 0x42cd50 B.EQ	42ccb0

(455) 0x42cd54 SBFM	X7, X6, #0, #31

(455) 0x42cd58 CMP	X17, X20

(455) 0x42cd5c MADD	X7, X13, X7, XZR

(455) 0x42cd60 B.HI	42cd80

(455) 0x42cd64 ADD	W22, W16, W10

(455) 0x42cd68 SBFM	X22, X22, #0, #31

(455) 0x42cd6c MADD	X22, X13, X22, X12

(455) 0x42cd70 ADD	X23, X22, X15

(455) 0x42cd74 CMP	X23, X22

(455) 0x42cd78 CCMP	X2, #0, #0, #9

(455) 0x42cd7c B.EQ	42ce20

(455) 0x42cd80 ORR	X22, XZR, XZR

(455) 0x42cd84 SUB	W23, W20, W22

(455) 0x42cd88 ANDS	X24, X23, #4160

(455) 0x42cd8c ORR	X23, XZR, X22

(455) 0x42cd90 B.EQ	42cdb8

(455) 0x42cd94 SUB	X23, X7, X22,LSL #3

(455) 0x42cd98 ADD	X25, X14, X7

(455) 0x42cd9c ADD	X26, X12, X23

(455) 0x42cda0 ORR	X23, XZR, X22

  (457) 0x42cda4 LDR	D0, [X25, X23,LSL #3]

  (457) 0x42cda8 ADD	X23, X23, #1

  (457) 0x42cdac SUBS	X24, X24, #1

  (457) 0x42cdb0 STR	D0, [X26], #504

  (457) 0x42cdb4 B.NE	42cda4

(455) 0x42cdb8 ORN	X22, XZR, X22

(455) 0x42cdbc ADD	X22, X22, X20

(455) 0x42cdc0 CMP	X22, #3

(455) 0x42cdc4 B.CC	42cd40

(455) 0x42cdc8 UBFM	X24, X23, #61, #60

(455) 0x42cdcc SUB	X23, X20, X23

(455) 0x42cdd0 SUB	X22, X7, X24

(455) 0x42cdd4 ADD	X7, X7, X24

(455) 0x42cdd8 ADD	X22, X21, X22

(455) 0x42cddc ADD	X7, X1, X7

  (456) 0x42cde0 LDUR	D0, [X7, #504]

  (456) 0x42cde4 SUBS	X23, X23, #4

  (456) 0x42cde8 STR	D0, [X22, #8]

  (456) 0x42cdec LDR	D0, [X7]

  (456) 0x42cdf0 STR	D0, [X22]

  (456) 0x42cdf4 LDR	D0, [X7, #8]

  (456) 0x42cdf8 STUR	D0, [X22, #504]

  (456) 0x42cdfc LDR	D0, [X7, #16]

  (456) 0x42ce00 ADD	X7, X7, #32

  (456) 0x42ce04 STUR	D0, [X22, #496]

  (456) 0x42ce08 SUB	X22, X22, #32

  (456) 0x42ce0c B.NE	42cde0

(455) 0x42ce10 B	42cd40

0x42ce14 HINT	#0

0x42ce18 HINT	#0

0x42ce1c HINT	#0

(455) 0x42ce20 UDIV	X22, X20, X11

(455) 0x42ce24 ORR	X25, XZR, X5

(455) 0x42ce28 ORR	X26, XZR, X4

(455) 0x42ce2c ORR	X27, XZR, X3

(455) 0x42ce30 ORR	X28, XZR, X14

(455) 0x42ce34 UMSUBL	X23, W22, W11, X20

(455) 0x42ce38 UMADDL	X22, W22, W11, XZR

(455) 0x42ce3c ORR	X24, XZR, X22

  (458) 0x42ce40 LD1B	{Z0.B}, P0/Z, [X28, X7]

  (458) 0x42ce44 LD1B	{Z1.B}, P0/Z, [X27, X7]

  (458) 0x42ce48 ADD	X28, X28, X18

  (458) 0x42ce4c ADD	X27, X27, X18

  (458) 0x42ce50 SUBS	X24, X24, X11

  (458) 0x42ce54 REV	Z0.D, Z0.D

  (458) 0x42ce58 ST1B	{Z0.B}, P0, [X26, X7]

  (458) 0x42ce5c REV	Z0.D, Z1.D

  (458) 0x42ce60 ADD	X26, X26, X0

  (458) 0x42ce64 ST1B	{Z0.B}, P0, [X25, X7]

  (458) 0x42ce68 ADD	X25, X25, X0

  (458) 0x42ce6c B.NE	42ce40

(455) 0x42ce70 CBNZ	X23, 42cd84

0x42ce74 B	42cd40

0x42ce78 HINT	#0

0x42ce7c HINT	#0

0x4375c8 HINT	#0

0x4375cc HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:236-239
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:236-239.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.67 to 0.71 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	48
loop length	192
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42cc10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42ccc0 <.omp_outlined..36+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <463c5c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #4032	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42cce0 <.omp_outlined..36+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 42cd40 <.omp_outlined..36+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	update_halo.cpp:236-239
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:236-239.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	48
loop length	192
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42cc10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42ccc0 <.omp_outlined..36+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <463c5c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #4032	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42cce0 <.omp_outlined..36+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 42cd40 <.omp_outlined..36+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..36–	0.01	0
▼Loop 455 - update_halo.cpp:236-239 - exec–	0	0
○Loop 457 - update_halo.cpp:238-239 - exec	0.01	0
○Loop 458 - update_halo.cpp:238-239 - exec	0	0
○Loop 456 - update_halo.cpp:238-239 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code