OV - exec - Function .omp

	Function: .omp_outlined..28	Module: exec	Source: update_halo.cpp:193-196	Coverage: 0.04%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 193 - 196

--------------------------------------------------------------------------------

193: #pragma omp parallel for simd

194:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

195:         for (int j = 0; j < depth; ++j) {

196:           field.energy1(1 - j, k) = field.energy1(2 + j, k);

0x42c2b0 SUB	SP, SP, #128

0x42c2b4 STP	X29, X30, [SP, #32]

0x42c2b8 STP	X28, X27, [SP, #48]

0x42c2bc STP	X26, X25, [SP, #64]

0x42c2c0 STP	X24, X23, [SP, #80]

0x42c2c4 STP	X22, X21, [SP, #96]

0x42c2c8 STP	X20, X19, [SP, #112]

0x42c2cc ADD	X29, SP, #32

0x42c2d0 LDR	W22, [X2]

0x42c2d4 LDR	W20, [X3]

0x42c2d8 LDR	W8, [X4]

0x42c2dc SUB	W9, W22, W20

0x42c2e0 ADD	W8, W8, W20

0x42c2e4 SUBS	W24, W8, W9

0x42c2e8 B.LT	42c360

0x42c2ec LDR	W19, [X0]

0x42c2f0 LDR	X23, [X5, #72]

0x42c2f4 LDR	X21, [X5, #88]

0x42c2f8 MOVZ	W8, #1

0x42c2fc ADRP	X0,

0x42c300 ADD	X0, X0, #3744

0x42c304 ADD	X3, SP, #16

0x42c308 SUB	X4, X29, #4

0x42c30c STP	W24, WZR, [X29, #504]

0x42c310 SUB	X5, X29, #8

0x42c314 SUB	X6, X29, #12

0x42c318 MOVZ	W2, #34

0x42c31c STUR	W8, [X29, #500]

0x42c320 STR	WZR, [SP, #16]

0x42c324 STR	W8, [SP]

0x42c328 MOVZ	W7, #1

0x42c32c ORR	W1, WZR, W19

0x42c330 BL	402f40

0x42c334 LDP	W8, W9, [X29, #504]

0x42c338 CMP	W8, W24

0x42c33c CSEL	W8, W8, W24, #3

0x42c340 ADD	W10, W8, #1

0x42c344 CMP	W9, W10

0x42c348 CCMP	W20, #1, #8, #3

0x42c34c B.GE	42c380

(425) 0x42c350 ORR	W1, WZR, W19

(425) 0x42c354 ADRP	X0,

(425) 0x42c358 ADD	X0, X0, #3768

(425) 0x42c35c BL	402d80

(425) 0x42c360 LDP	X20, X19, [SP, #112]

(425) 0x42c364 LDP	X22, X21, [SP, #96]

(425) 0x42c368 LDP	X24, X23, [SP, #80]

(425) 0x42c36c LDP	X26, X25, [SP, #64]

(425) 0x42c370 LDP	X28, X27, [SP, #48]

(425) 0x42c374 LDP	X29, X30, [SP, #32]

(425) 0x42c378 ADD	SP, SP, #128

(425) 0x42c37c RET

(425) 0x42c380 ADD	W15, W9, W22

(425) 0x42c384 CNTW	X11, ALL

(425) 0x42c388 SUB	X2, X20, #1

(425) 0x42c38c ADD	X14, X21, #16

(425) 0x42c390 MOVZ	W17, #12

(425) 0x42c394 RDVL	X4, #1

(425) 0x42c398 ORR	W10, WZR, WZR

(425) 0x42c39c ADD	X12, X21, #8

(425) 0x42c3a0 UBFM	X13, X23, #61, #60

(425) 0x42c3a4 RDVL	X18, #2

(425) 0x42c3a8 RDVL	X0, #62

(425) 0x42c3ac ADD	X1, X21, #24

(425) 0x42c3b0 CMP	X11, #12

(425) 0x42c3b4 SUB	W16, W15, W20

(425) 0x42c3b8 SUB	X15, XZR, X2,LSL #3

(425) 0x42c3bc UBFM	X2, X2, #61, #63

(425) 0x42c3c0 CSEL	X17, X11, X17, #8

(425) 0x42c3c4 ADDVL	X3, X14, #1

(425) 0x42c3c8 SUB	X4, X14, X4

(425) 0x42c3cc ADD	W16, W16, #1

(425) 0x42c3d0 ADDVL	X5, X14, #62

(425) 0x42c3d4 PTRUE	P0.B, ALL

(425) 0x42c3d8 ORR	W6, WZR, W16

(425) 0x42c3dc B	42c3f4

(425) 0x42c3e0 CMP	W9, W8

(425) 0x42c3e4 ADD	W9, W9, #1

(425) 0x42c3e8 ADD	W10, W10, #1

(425) 0x42c3ec ADD	W6, W6, #1

(425) 0x42c3f0 B.EQ	42c350

(425) 0x42c3f4 SBFM	X7, X6, #0, #31

(425) 0x42c3f8 CMP	X17, X20

(425) 0x42c3fc MADD	X7, X13, X7, XZR

(425) 0x42c400 B.HI	42c420

(425) 0x42c404 ADD	W22, W16, W10

(425) 0x42c408 SBFM	X22, X22, #0, #31

(425) 0x42c40c MADD	X22, X13, X22, X12

(425) 0x42c410 ADD	X23, X22, X15

(425) 0x42c414 CMP	X23, X22

(425) 0x42c418 CCMP	X2, #0, #0, #9

(425) 0x42c41c B.EQ	42c4c0

(425) 0x42c420 ORR	X22, XZR, XZR

(425) 0x42c424 SUB	W23, W20, W22

(425) 0x42c428 ANDS	X24, X23, #4160

(425) 0x42c42c ORR	X23, XZR, X22

(425) 0x42c430 B.EQ	42c458

(425) 0x42c434 SUB	X23, X7, X22,LSL #3

(425) 0x42c438 ADD	X25, X14, X7

(425) 0x42c43c ADD	X26, X12, X23

(425) 0x42c440 ORR	X23, XZR, X22

  (427) 0x42c444 LDR	D0, [X25, X23,LSL #3]

  (427) 0x42c448 ADD	X23, X23, #1

  (427) 0x42c44c SUBS	X24, X24, #1

  (427) 0x42c450 STR	D0, [X26], #504

  (427) 0x42c454 B.NE	42c444

(425) 0x42c458 ORN	X22, XZR, X22

(425) 0x42c45c ADD	X22, X22, X20

(425) 0x42c460 CMP	X22, #3

(425) 0x42c464 B.CC	42c3e0

(425) 0x42c468 UBFM	X24, X23, #61, #60

(425) 0x42c46c SUB	X23, X20, X23

(425) 0x42c470 SUB	X22, X7, X24

(425) 0x42c474 ADD	X7, X7, X24

(425) 0x42c478 ADD	X22, X21, X22

(425) 0x42c47c ADD	X7, X1, X7

  (426) 0x42c480 LDUR	D0, [X7, #504]

  (426) 0x42c484 SUBS	X23, X23, #4

  (426) 0x42c488 STR	D0, [X22, #8]

  (426) 0x42c48c LDR	D0, [X7]

  (426) 0x42c490 STR	D0, [X22]

  (426) 0x42c494 LDR	D0, [X7, #8]

  (426) 0x42c498 STUR	D0, [X22, #504]

  (426) 0x42c49c LDR	D0, [X7, #16]

  (426) 0x42c4a0 ADD	X7, X7, #32

  (426) 0x42c4a4 STUR	D0, [X22, #496]

  (426) 0x42c4a8 SUB	X22, X22, #32

  (426) 0x42c4ac B.NE	42c480

(425) 0x42c4b0 B	42c3e0

0x42c4b4 HINT	#0

0x42c4b8 HINT	#0

0x42c4bc HINT	#0

(425) 0x42c4c0 UDIV	X22, X20, X11

(425) 0x42c4c4 ORR	X25, XZR, X5

(425) 0x42c4c8 ORR	X26, XZR, X4

(425) 0x42c4cc ORR	X27, XZR, X3

(425) 0x42c4d0 ORR	X28, XZR, X14

(425) 0x42c4d4 UMSUBL	X23, W22, W11, X20

(425) 0x42c4d8 UMADDL	X22, W22, W11, XZR

(425) 0x42c4dc ORR	X24, XZR, X22

  (428) 0x42c4e0 LD1B	{Z0.B}, P0/Z, [X28, X7]

  (428) 0x42c4e4 LD1B	{Z1.B}, P0/Z, [X27, X7]

  (428) 0x42c4e8 ADD	X28, X28, X18

  (428) 0x42c4ec ADD	X27, X27, X18

  (428) 0x42c4f0 SUBS	X24, X24, X11

  (428) 0x42c4f4 REV	Z0.D, Z0.D

  (428) 0x42c4f8 ST1B	{Z0.B}, P0, [X26, X7]

  (428) 0x42c4fc REV	Z0.D, Z1.D

  (428) 0x42c500 ADD	X26, X26, X0

  (428) 0x42c504 ST1B	{Z0.B}, P0, [X25, X7]

  (428) 0x42c508 ADD	X25, X25, X0

  (428) 0x42c50c B.NE	42c4e0

(425) 0x42c510 CBNZ	X23, 42c424

0x42c514 B	42c3e0

0x42c518 HINT	#0

0x42c51c HINT	#0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:193-196
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:193-196.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.67 to 0.71 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	46
loop length	184
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42c2b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42c360 <.omp_outlined..28+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4632fc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3744	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42c380 <.omp_outlined..28+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 42c3e0 <.omp_outlined..28+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	update_halo.cpp:193-196
Module	exec

The function is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:193-196.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.67 to 0.50 cycles (11.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 116 bytes.

General properties

nb instructions	46
loop length	184
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00
cycles	2.00	2.00	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	5.67	5.67	5.67	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	5.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.67 cycles. At this rate:

7% of peak load performance is reached (7.06 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42c2b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W20, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W24, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42c360 <.omp_outlined..28+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X5, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X5, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4632fc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3744	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, WZR, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR W8, [X29, #500]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR WZR, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 402f40 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP W8, W9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W8, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL W8, W8, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP W20, #1, #8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.GE 42c380 <.omp_outlined..28+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
B 42c3e0 <.omp_outlined..28+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..28–	0.04	0.02
▼Loop 425 - update_halo.cpp:193-196 - exec–	0	0
○Loop 427 - update_halo.cpp:195-196 - exec	0.04	0.02
○Loop 426 - update_halo.cpp:195-196 - exec	0	0
○Loop 428 - update_halo.cpp:195-196 - exec	0	0

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ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code