OV - exec - Loop 485

	Loop Id: 485	Module: exec	Source: update_halo.cpp:271-272 [...]	Coverage: 0.02%

0x4306c0 ADD	X16, X4, X21

0x4306c4 ADD	X17, X4, X22

0x4306c8 ANDS	W5, W20, #128

0x4306cc ADD	X1, X18, X16,LSL #3

0x4306d0 MOVZ	W3, #0

0x4306d4 ADD	X2, X18, X17,LSL #3

0x4306d8 B.EQ	4307a0

0x4306dc CMP	W5, #1

0x4306e0 B.EQ	430784

0x4306e4 CMP	W5, #2

0x4306e8 B.EQ	430770

0x4306ec CMP	W5, #3

0x4306f0 B.EQ	43075c

0x4306f4 CMP	W5, #4

0x4306f8 B.EQ	430748

0x4306fc CMP	W5, #5

0x430700 B.EQ	430734

0x430704 CMP	W5, #6

0x430708 B.EQ	430720

0x43070c LDR	D0, [X18, X16,LSL #3]

0x430710 ADD	X1, X1, X0

0x430714 SUB	X2, X2, X0

0x430718 MOVZ	W3, #1

0x43071c STR	D0, [X18, X17,LSL #3]

0x430720 LDR	D1, [X1]

0x430724 ADD	W3, W3, #1

0x430728 ADD	X1, X1, X0

0x43072c STR	D1, [X2]

0x430730 SUB	X2, X2, X0

0x430734 LDR	D2, [X1]

0x430738 ADD	W3, W3, #1

0x43073c ADD	X1, X1, X0

0x430740 STR	D2, [X2]

0x430744 SUB	X2, X2, X0

0x430748 LDR	D3, [X1]

0x43074c ADD	W3, W3, #1

0x430750 ADD	X1, X1, X0

0x430754 STR	D3, [X2]

0x430758 SUB	X2, X2, X0

0x43075c LDR	D4, [X1]

0x430760 ADD	W3, W3, #1

0x430764 ADD	X1, X1, X0

0x430768 STR	D4, [X2]

0x43076c SUB	X2, X2, X0

0x430770 LDR	D5, [X1]

0x430774 ADD	W3, W3, #1

0x430778 ADD	X1, X1, X0

0x43077c STR	D5, [X2]

0x430780 SUB	X2, X2, X0

0x430784 LDR	D6, [X1]

0x430788 ADD	W3, W3, #1

0x43078c ADD	X1, X1, X0

0x430790 STR	D6, [X2]

0x430794 SUB	X2, X2, X0

0x430798 CMP	W20, W3

0x43079c B.EQ	430828

  (484) 0x4307a0 LDR	D7, [X1]

  (484) 0x4307a4 SUB	X17, X2, X0

  (484) 0x4307a8 ADD	X16, X1, X0

  (484) 0x4307ac SUB	X15, X17, X0

  (484) 0x4307b0 ADD	X14, X16, X0

  (484) 0x4307b4 SUB	X13, X15, X0

  (484) 0x4307b8 ADD	X12, X14, X0

  (484) 0x4307bc SUB	X11, X13, X0

  (484) 0x4307c0 ADD	X10, X12, X0

  (484) 0x4307c4 SUB	X9, X11, X0

  (484) 0x4307c8 ADD	X8, X10, X0

  (484) 0x4307cc SUB	X7, X9, X0

  (484) 0x4307d0 ADD	X6, X8, X0

  (484) 0x4307d4 STR	D7, [X2]

  (484) 0x4307d8 SUB	X5, X7, X0

  (484) 0x4307dc ADD	W3, W3, #8

  (484) 0x4307e0 LDR	D16, [X1, X0]

  (484) 0x4307e4 SUB	X2, X5, X0

  (484) 0x4307e8 ADD	X1, X6, X0,LSL #1

  (484) 0x4307ec STR	D16, [X17]

  (484) 0x4307f0 LDR	D17, [X16, X0]

  (484) 0x4307f4 STR	D17, [X15]

  (484) 0x4307f8 LDR	D18, [X14, X0]

  (484) 0x4307fc STR	D18, [X13]

  (484) 0x430800 LDR	D19, [X12, X0]

  (484) 0x430804 STR	D19, [X11]

  (484) 0x430808 LDR	D20, [X10, X0]

  (484) 0x43080c STR	D20, [X9]

  (484) 0x430810 LDR	D21, [X8, X0]

  (484) 0x430814 STR	D21, [X7]

  (484) 0x430818 LDR	D22, [X6, X0]

  (484) 0x43081c STR	D22, [X5]

  (484) 0x430820 CMP	W20, W3

  (484) 0x430824 B.NE	4307a0

0x430828 ADD	X4, X4, #1

0x43082c ADD	W3, W30, W4

0x430830 CMP	W19, W3

0x430834 B.GT	4306c0

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 271 - 272

--------------------------------------------------------------------------------

271:         for (int k = 0; k < depth; ++k) {

272:           field.viscosity(j, y_max + 2 + k) = field.viscosity(j, y_max + 1 - k);

Path /

Metric	Value
CQA speedup if no scalar integer	1.91
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.66
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.21]
Source	update_halo.cpp:271-272
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.25
CQA cycles if no scalar integer	4.83
CQA cycles if FP arith vectorized	9.25
CQA cycles if fully vectorized	1.21
Front-end cycles	7.50
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	9.25
P2 cycles	9.25
P3 cycles	9.25
P4 cycles	9.25
P5 cycles	3.50
P6 cycles	3.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.83
P10 cycles	4.50
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	60.00
Nb loads	NA
Nb stores	7.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.11
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	20.65
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.91
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.66
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.21]
Source	update_halo.cpp:271-272
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.25
CQA cycles if no scalar integer	4.83
CQA cycles if FP arith vectorized	9.25
CQA cycles if fully vectorized	1.21
Front-end cycles	7.50
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	9.25
P2 cycles	9.25
P3 cycles	9.25
P4 cycles	9.25
P5 cycles	3.50
P6 cycles	3.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.83
P10 cycles	4.50
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	60.00
Nb loads	NA
Nb stores	7.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.11
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	20.65
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.21]
Source file and lines	update_halo.cpp:271-272
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:271-272

Analyzed code is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:271-272.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=15
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 15 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.25 to 4.83 cycles (1.91x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 20% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 9.25 to 1.21 cycles (7.66x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	9.25	9.25	9.25	9.25	3.50	3.50	0.00	0.00	4.83	4.50	4.67	0.00	0.00
cycles	4.50	4.50	9.25	9.25	9.25	9.25	3.50	3.50	0.00	0.00	4.83	4.50	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Overall L1	9.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.25 cycles. At this rate:

6% of peak load performance is reached (6.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.05 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4306c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
ADD X16, X4, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X17, X4, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS W5, W20, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
ADD X1, X18, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X18, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B.EQ 4307a0 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 430784 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 430770 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 43075c <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W5, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 430748 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W5, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 430734 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W5, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 430720 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X18, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D0, [X18, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D1, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D1, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D2, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D2, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D3, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D3, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D4, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D4, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D5, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D5, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D6, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D6, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 430828 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W30, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W19, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4306c0 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.21]
Source file and lines	update_halo.cpp:271-272
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:271-272

Analyzed code is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:271-272.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=15
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.25 to 4.83 cycles (1.91x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	9.25	9.25	9.25	9.25	3.50	3.50	0.00	0.00	4.83	4.50	4.67	0.00	0.00
cycles	4.50	4.50	9.25	9.25	9.25	9.25	3.50	3.50	0.00	0.00	4.83	4.50	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Overall L1	9.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.25 cycles. At this rate:

6% of peak load performance is reached (6.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.05 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4306c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
ADD X16, X4, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X17, X4, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS W5, W20, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
ADD X1, X18, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X18, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B.EQ 4307a0 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 430784 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 430770 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W5, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 43075c <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W5, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 430748 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W5, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 430734 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W5, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 430720 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X18, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D0, [X18, X17,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D1, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D1, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D2, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D2, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D3, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D3, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D4, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D4, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D5, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D5, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D6, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D6, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W20, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 430828 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W30, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W19, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4306c0 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.21+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code