OV - exec - Loop 477

  (479) 0x430240 MADD	W8, W6, W1, W7

  (479) 0x430244 ADD	W9, W6, W8

  (479) 0x430248 CMP	W8, W9

  (479) 0x43024c B.GE	4303d4

  (479) 0x430250 ADD	W10, W19, W8

  (479) 0x430254 LDR	W13, [X22, #8]

  (479) 0x430258 ADD	W19, W19, W9

  (479) 0x43025c LDR	X11, [X22]

  (479) 0x430260 CMP	W20, #0

  (479) 0x430264 B.LE	4303d4

0x430268 ADD	W14, W13, #1

0x43026c SBFM	X5, X10, #0, #31

0x430270 LDR	X16, [X11, #96]

0x430274 SBFM	X14, X14, #0, #31

0x430278 SBFM	X13, X13, #0, #31

0x43027c MOVZ	W15, #0

0x430280 LDR	X6, [X11, #112]

0x430284 MADD	X12, X16, X5, XZR

0x430288 SUB	W17, W20, #1

0x43028c MOVZ	X0, #1

0x430290 AND	W18, W17, #128

0x430294 ADD	X30, X14, X12

0x430298 ADD	X22, X13, X12

0x43029c UBFM	X21, X22, #61, #60

0x4302a0 ADD	X4, X6, X30,LSL #3

0x4302a4 LDR	D0, [X6, X30,LSL #3]

0x4302a8 ADD	X2, X21, #16

0x4302ac ADD	X3, X6, X2

0x4302b0 SUB	X1, X4, #8

0x4302b4 STR	D0, [X6, X2]

0x4302b8 CMP	W20, #1

0x4302bc B.LE	4303c4

0x4302c0 CBZ	W18, 430354

  (478) 0x430354 ORR	X17, XZR, X1

  (478) 0x430358 ADD	X18, X0, #1

  (478) 0x43035c ADD	X12, X0, #2

  (478) 0x430360 ADD	X11, X0, #3

  (478) 0x430364 LDR	D16, [X17], #504

  (478) 0x430368 ADD	X10, X0, #4

  (478) 0x43036c ADD	X9, X0, #5

  (478) 0x430370 ADD	X8, X0, #6

  (478) 0x430374 ADD	X7, X0, #7

  (478) 0x430378 SUB	X1, X1, #64

  (478) 0x43037c STR	D16, [X3, X0,LSL #3]

  (478) 0x430380 ADD	X0, X0, #8

  (478) 0x430384 LDR	D17, [X1, #56]

  (478) 0x430388 STR	D17, [X3, X18,LSL #3]

  (478) 0x43038c LDUR	D18, [X17, #504]

  (478) 0x430390 STR	D18, [X3, X12,LSL #3]

  (478) 0x430394 LDR	D19, [X1, #40]

  (478) 0x430398 STR	D19, [X3, X11,LSL #3]

  (478) 0x43039c LDR	D20, [X1, #32]

  (478) 0x4303a0 STR	D20, [X3, X10,LSL #3]

  (478) 0x4303a4 LDR	D21, [X1, #24]

  (478) 0x4303a8 STR	D21, [X3, X9,LSL #3]

  (478) 0x4303ac LDR	D22, [X1, #16]

  (478) 0x4303b0 STR	D22, [X3, X8,LSL #3]

  (478) 0x4303b4 LDR	D23, [X1, #8]

  (478) 0x4303b8 STR	D23, [X3, X7,LSL #3]

  (478) 0x4303bc CMP	W20, W0

  (478) 0x4303c0 B.GT	430354

0x4303c4 ADD	X5, X5, #1

0x4303c8 ADD	W30, W15, W5

0x4303cc CMP	W19, W30

0x4303d0 B.GT	430284

  (479) 0x4303d4 LDP	X19, X20, [SP, #16]

  (479) 0x4303d8 LDP	X21, X22, [SP, #32]

  (479) 0x4303dc LDP	X29, X30, [SP], #48

  (479) 0x4303e0 RET

  (479) 0x4303e4 ADD	W6, W6, #1

  (479) 0x4303e8 MOVZ	W7, #0

  (479) 0x4303ec B	430240

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 246 - 249

--------------------------------------------------------------------------------

246: #pragma omp parallel for simd

247:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

248:         for (int j = 0; j < depth; ++j) {

249:           field.pressure(x_max + 2 + j, k) = field.pressure(x_max + 1 - j, k);

Path /

Metric	Value
CQA speedup if no scalar integer	6.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.15
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.19]
Source	context.h:69-69,update_halo.cpp:248-249
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	0.83
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	0.81
Front-end cycles	3.38
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	5.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	5.00
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.50
P10 cycles	1.17
P11 cycles	1.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	27.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.40
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	20.54
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.43
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.63

Metric	Value
CQA speedup if no scalar integer	6.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.15
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.19]
Source	context.h:69-69,update_halo.cpp:248-249
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	0.83
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	0.81
Front-end cycles	3.38
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	5.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	5.00
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.50
P10 cycles	1.17
P11 cycles	1.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	27.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.40
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	20.54
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.43
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.63

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.19]
Source file and lines	update_halo.cpp:246-249
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:246-249

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.00 to 0.83 cycles (6.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 20% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 0.81 cycles (6.15x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 24 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	5.00	5.00	5.00	5.00	0.50	0.50	0.00	0.00	1.50	1.17	1.33	0.00	0.00
cycles	1.50	1.50	5.00	5.00	5.00	5.00	0.50	0.50	0.00	0.00	1.50	1.17	1.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.38
Overall L1	5.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

5% of peak load performance is reached (4.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4303c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
ADD W14, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X5, X10, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X11, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SBFM X14, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X13, X13, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X6, [X11, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X12, X16, X5, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
SUB W17, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
AND W18, W17, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X30, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X22, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X21, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X6, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D0, [X6, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X2, X21, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X6, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X1, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D0, [X6, X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4303c4 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W18, 430354 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W30, W15, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W19, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 430284 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.19]
Source file and lines	update_halo.cpp:246-249
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:246-249

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.00 to 0.83 cycles (6.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 20% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 0.81 cycles (6.15x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 24 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	5.00	5.00	5.00	5.00	0.50	0.50	0.00	0.00	1.50	1.17	1.33	0.00	0.00
cycles	1.50	1.50	5.00	5.00	5.00	5.00	0.50	0.50	0.00	0.00	1.50	1.17	1.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.38
Overall L1	5.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

5% of peak load performance is reached (4.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4303c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
ADD W14, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X5, X10, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X11, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SBFM X14, X14, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X13, X13, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X6, [X11, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X12, X16, X5, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
SUB W17, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
AND W18, W17, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X30, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X22, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X21, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X6, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D0, [X6, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X2, X21, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X6, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X1, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D0, [X6, X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4303c4 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W18, 430354 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W30, W15, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W19, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 430284 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.19+0x98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code