OV - exec - Loop 464

	Loop Id: 464	Module: exec	Source: update_halo.cpp:195-196 [...]	Coverage: 0.02%

0x42f7c0 MADD	X16, X14, X4, XZR

0x42f7c4 ADD	X17, X21, X16

0x42f7c8 ADD	X0, X12, X16,LSL #3

0x42f7cc UBFM	X18, X16, #60, #59

0x42f7d0 ADD	X5, X13, X17,LSL #3

0x42f7d4 ADD	X1, X18, #8

0x42f7d8 SUB	X30, X5, X0

0x42f7dc SUB	X22, X30, #8

0x42f7e0 UBFM	X20, X22, #3, #63

0x42f7e4 ADD	X2, X20, #1

0x42f7e8 ANDS	X6, X2, #4224

0x42f7ec B.EQ	42f898

0x42f7f0 CMP	X6, #1

0x42f7f4 B.EQ	42f880

0x42f7f8 CMP	X6, #2

0x42f7fc B.EQ	42f870

0x42f800 CMP	X6, #3

0x42f804 B.EQ	42f860

0x42f808 CMP	X6, #4

0x42f80c B.EQ	42f850

0x42f810 CMP	X6, #5

0x42f814 B.EQ	42f840

0x42f818 CMP	X6, #6

0x42f81c B.EQ	42f830

0x42f820 LDR	D0, [X0, #16]

0x42f824 SUB	X7, X1, X0

0x42f828 ADD	X0, X0, #8

0x42f82c STR	D0, [X7, X3]

0x42f830 LDR	D1, [X0, #16]

0x42f834 SUB	X8, X1, X0

0x42f838 ADD	X0, X0, #8

0x42f83c STR	D1, [X8, X3]

0x42f840 LDR	D2, [X0, #16]

0x42f844 SUB	X9, X1, X0

0x42f848 ADD	X0, X0, #8

0x42f84c STR	D2, [X9, X3]

0x42f850 LDR	D3, [X0, #16]

0x42f854 SUB	X10, X1, X0

0x42f858 ADD	X0, X0, #8

0x42f85c STR	D3, [X10, X3]

0x42f860 LDR	D4, [X0, #16]

0x42f864 SUB	X11, X1, X0

0x42f868 ADD	X0, X0, #8

0x42f86c STR	D4, [X11, X3]

0x42f870 LDR	D5, [X0, #16]

0x42f874 SUB	X16, X1, X0

0x42f878 ADD	X0, X0, #8

0x42f87c STR	D5, [X16, X3]

0x42f880 LDR	D6, [X0, #16]

0x42f884 SUB	X17, X1, X0

0x42f888 ADD	X0, X0, #8

0x42f88c STR	D6, [X17, X3]

0x42f890 CMP	X5, X0

0x42f894 B.EQ	42f920

  (463) 0x42f898 LDR	D7, [X0, #16]

  (463) 0x42f89c SUB	X6, X1, X0

  (463) 0x42f8a0 ADD	X18, X0, #8

  (463) 0x42f8a4 ADD	X11, X0, #16

  (463) 0x42f8a8 SUB	X30, X1, X18

  (463) 0x42f8ac ADD	X10, X0, #24

  (463) 0x42f8b0 SUB	X22, X1, X11

  (463) 0x42f8b4 ADD	X9, X0, #32

  (463) 0x42f8b8 SUB	X20, X1, X10

  (463) 0x42f8bc ADD	X8, X0, #40

  (463) 0x42f8c0 SUB	X18, X1, X9

  (463) 0x42f8c4 ADD	X7, X0, #48

  (463) 0x42f8c8 SUB	X17, X1, X8

  (463) 0x42f8cc STR	D7, [X6, X3]

  (463) 0x42f8d0 SUB	X16, X1, X7

  (463) 0x42f8d4 ADD	X6, X0, #56

  (463) 0x42f8d8 LDR	D16, [X0, #24]

  (463) 0x42f8dc SUB	X2, X1, X6

  (463) 0x42f8e0 ADD	X0, X0, #64

  (463) 0x42f8e4 STR	D16, [X30, X3]

  (463) 0x42f8e8 LDR	D17, [X11, #16]

  (463) 0x42f8ec STR	D17, [X22, X3]

  (463) 0x42f8f0 LDR	D18, [X10, #16]

  (463) 0x42f8f4 STR	D18, [X20, X3]

  (463) 0x42f8f8 LDR	D19, [X9, #16]

  (463) 0x42f8fc STR	D19, [X18, X3]

  (463) 0x42f900 LDR	D20, [X8, #16]

  (463) 0x42f904 STR	D20, [X17, X3]

  (463) 0x42f908 LDR	D21, [X7, #16]

  (463) 0x42f90c STR	D21, [X16, X3]

  (463) 0x42f910 LDR	D22, [X6, #16]

  (463) 0x42f914 STR	D22, [X2, X3]

  (463) 0x42f918 CMP	X5, X0

  (463) 0x42f91c B.NE	42f898

0x42f920 ADD	X4, X4, #1

0x42f924 ADD	W5, W15, W4

0x42f928 CMP	W19, W5

0x42f92c B.GT	42f7c0

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 195 - 196

--------------------------------------------------------------------------------

195:         for (int j = 0; j < depth; ++j) {

196:           field.energy1(1 - j, k) = field.energy1(2 + j, k);

Path /

Metric	Value
CQA speedup if no scalar integer	1.81
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.14]
Source	context.h:69-69,update_halo.cpp:195-196
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.75
CQA cycles if no scalar integer	4.83
CQA cycles if FP arith vectorized	8.75
CQA cycles if fully vectorized	2.19
Front-end cycles	7.25
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	8.75
P2 cycles	8.75
P3 cycles	8.75
P4 cycles	8.75
P5 cycles	3.50
P6 cycles	3.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.83
P10 cycles	4.50
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	58.00
Nb loads	NA
Nb stores	7.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.80
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.81
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.14]
Source	context.h:69-69,update_halo.cpp:195-196
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.75
CQA cycles if no scalar integer	4.83
CQA cycles if FP arith vectorized	8.75
CQA cycles if fully vectorized	2.19
Front-end cycles	7.25
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	8.75
P2 cycles	8.75
P3 cycles	8.75
P4 cycles	8.75
P5 cycles	3.50
P6 cycles	3.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.83
P10 cycles	4.50
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	58.00
Nb loads	NA
Nb stores	7.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.80
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.14]
Source file and lines	update_halo.cpp:195-196
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:195-196

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=15
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 15 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.75 to 4.83 cycles (1.81x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.75 to 2.19 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	58
loop length	232
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	8.75	8.75	8.75	8.75	3.50	3.50	0.00	0.00	4.83	4.50	4.67	0.00	0.00
cycles	4.50	4.50	8.75	8.75	8.75	8.75	3.50	3.50	0.00	0.00	4.83	4.50	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.25
Overall L1	8.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.75 cycles. At this rate:

6% of peak load performance is reached (6.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42f7c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
MADD X16, X14, X4, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X17, X21, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X12, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X18, X16, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X13, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X30, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X22, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X20, X22, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X6, X2, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f898 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f880 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f870 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f860 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f850 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f840 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f830 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB X7, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D0, [X7, X3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D1, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB X8, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D1, [X8, X3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D2, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB X9, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D2, [X9, X3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D3, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB X10, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D3, [X10, X3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D4, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB X11, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D4, [X11, X3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D5, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB X16, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D5, [X16, X3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D6, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB X17, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D6, [X17, X3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f920 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W5, W15, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W19, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 42f7c0 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.14]
Source file and lines	update_halo.cpp:195-196
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:195-196

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=15
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.75 to 4.83 cycles (1.81x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.75 to 2.19 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	58
loop length	232
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	8.75	8.75	8.75	8.75	3.50	3.50	0.00	0.00	4.83	4.50	4.67	0.00	0.00
cycles	4.50	4.50	8.75	8.75	8.75	8.75	3.50	3.50	0.00	0.00	4.83	4.50	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.25
Overall L1	8.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.75 cycles. At this rate:

6% of peak load performance is reached (6.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42f7c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
MADD X16, X14, X4, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X17, X21, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X12, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X18, X16, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X13, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X30, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X22, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X20, X22, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X6, X2, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f898 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0x178>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f880 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f870 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f860 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f850 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f840 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f830 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB X7, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D0, [X7, X3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D1, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB X8, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D1, [X8, X3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D2, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB X9, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D2, [X9, X3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D3, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB X10, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D3, [X10, X3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D4, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB X11, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D4, [X11, X3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D5, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB X16, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D5, [X16, X3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D6, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB X17, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D6, [X17, X3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f920 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W5, W15, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W19, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 42f7c0 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.14+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code