OV - exec - Loop 458

	Loop Id: 458	Module: exec	Source: update_halo.cpp:175-176 [...]	Coverage: 0.02%

0x42f340 ADD	X13, X4, X22

0x42f344 ADD	X14, X21, X4

0x42f348 ANDS	W15, W19, #128

0x42f34c ADD	X1, X20, X13,LSL #3

0x42f350 MOVZ	W3, #0

0x42f354 ADD	X2, X20, X14,LSL #3

0x42f358 B.EQ	42f420

0x42f35c CMP	W15, #1

0x42f360 B.EQ	42f404

0x42f364 CMP	W15, #2

0x42f368 B.EQ	42f3f0

0x42f36c CMP	W15, #3

0x42f370 B.EQ	42f3dc

0x42f374 CMP	W15, #4

0x42f378 B.EQ	42f3c8

0x42f37c CMP	W15, #5

0x42f380 B.EQ	42f3b4

0x42f384 CMP	W15, #6

0x42f388 B.EQ	42f3a0

0x42f38c LDR	D0, [X20, X13,LSL #3]

0x42f390 ADD	X1, X1, X0

0x42f394 SUB	X2, X2, X0

0x42f398 MOVZ	W3, #1

0x42f39c STR	D0, [X20, X14,LSL #3]

0x42f3a0 LDR	D1, [X1]

0x42f3a4 ADD	W3, W3, #1

0x42f3a8 ADD	X1, X1, X0

0x42f3ac STR	D1, [X2]

0x42f3b0 SUB	X2, X2, X0

0x42f3b4 LDR	D2, [X1]

0x42f3b8 ADD	W3, W3, #1

0x42f3bc ADD	X1, X1, X0

0x42f3c0 STR	D2, [X2]

0x42f3c4 SUB	X2, X2, X0

0x42f3c8 LDR	D3, [X1]

0x42f3cc ADD	W3, W3, #1

0x42f3d0 ADD	X1, X1, X0

0x42f3d4 STR	D3, [X2]

0x42f3d8 SUB	X2, X2, X0

0x42f3dc LDR	D4, [X1]

0x42f3e0 ADD	W3, W3, #1

0x42f3e4 ADD	X1, X1, X0

0x42f3e8 STR	D4, [X2]

0x42f3ec SUB	X2, X2, X0

0x42f3f0 LDR	D5, [X1]

0x42f3f4 ADD	W3, W3, #1

0x42f3f8 ADD	X1, X1, X0

0x42f3fc STR	D5, [X2]

0x42f400 SUB	X2, X2, X0

0x42f404 LDR	D6, [X1]

0x42f408 ADD	W3, W3, #1

0x42f40c ADD	X1, X1, X0

0x42f410 STR	D6, [X2]

0x42f414 SUB	X2, X2, X0

0x42f418 CMP	W19, W3

0x42f41c B.EQ	42f4a8

  (457) 0x42f420 LDR	D7, [X1]

  (457) 0x42f424 SUB	X18, X2, X0

  (457) 0x42f428 ADD	X17, X1, X0

  (457) 0x42f42c SUB	X16, X18, X0

  (457) 0x42f430 ADD	X15, X17, X0

  (457) 0x42f434 SUB	X14, X16, X0

  (457) 0x42f438 ADD	X13, X15, X0

  (457) 0x42f43c SUB	X12, X14, X0

  (457) 0x42f440 ADD	X11, X13, X0

  (457) 0x42f444 SUB	X10, X12, X0

  (457) 0x42f448 ADD	X9, X11, X0

  (457) 0x42f44c SUB	X8, X10, X0

  (457) 0x42f450 ADD	X7, X9, X0

  (457) 0x42f454 STR	D7, [X2]

  (457) 0x42f458 SUB	X5, X8, X0

  (457) 0x42f45c ADD	W3, W3, #8

  (457) 0x42f460 LDR	D16, [X1, X0]

  (457) 0x42f464 SUB	X2, X5, X0

  (457) 0x42f468 ADD	X1, X7, X0,LSL #1

  (457) 0x42f46c STR	D16, [X18]

  (457) 0x42f470 LDR	D17, [X17, X0]

  (457) 0x42f474 STR	D17, [X16]

  (457) 0x42f478 LDR	D18, [X15, X0]

  (457) 0x42f47c STR	D18, [X14]

  (457) 0x42f480 LDR	D19, [X13, X0]

  (457) 0x42f484 STR	D19, [X12]

  (457) 0x42f488 LDR	D20, [X11, X0]

  (457) 0x42f48c STR	D20, [X10]

  (457) 0x42f490 LDR	D21, [X9, X0]

  (457) 0x42f494 STR	D21, [X8]

  (457) 0x42f498 LDR	D22, [X7, X0]

  (457) 0x42f49c STR	D22, [X5]

  (457) 0x42f4a0 CMP	W19, W3

  (457) 0x42f4a4 B.NE	42f420

0x42f4a8 ADD	X4, X4, #1

0x42f4ac ADD	W3, W30, W4

0x42f4b0 CMP	W6, W3

0x42f4b4 B.GT	42f340

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 175 - 176

--------------------------------------------------------------------------------

175:         for (int k = 0; k < depth; ++k) {

176:           field.energy1(j, 1 - k) = field.energy1(j, 2 + k);

Path /

Metric	Value
CQA speedup if no scalar integer	1.91
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.66
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.12]
Source	update_halo.cpp:175-176
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.25
CQA cycles if no scalar integer	4.83
CQA cycles if FP arith vectorized	9.25
CQA cycles if fully vectorized	1.21
Front-end cycles	7.50
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	9.25
P2 cycles	9.25
P3 cycles	9.25
P4 cycles	9.25
P5 cycles	3.50
P6 cycles	3.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.83
P10 cycles	4.50
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	60.00
Nb loads	NA
Nb stores	7.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.11
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	20.65
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.91
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.66
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.12]
Source	update_halo.cpp:175-176
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.25
CQA cycles if no scalar integer	4.83
CQA cycles if FP arith vectorized	9.25
CQA cycles if fully vectorized	1.21
Front-end cycles	7.50
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	9.25
P2 cycles	9.25
P3 cycles	9.25
P4 cycles	9.25
P5 cycles	3.50
P6 cycles	3.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.83
P10 cycles	4.50
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	60.00
Nb loads	NA
Nb stores	7.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.11
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	20.65
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.12]
Source file and lines	update_halo.cpp:175-176
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:175-176

Analyzed code is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:175-176.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=15
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 15 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.25 to 4.83 cycles (1.91x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 20% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 9.25 to 1.21 cycles (7.66x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	9.25	9.25	9.25	9.25	3.50	3.50	0.00	0.00	4.83	4.50	4.67	0.00	0.00
cycles	4.50	4.50	9.25	9.25	9.25	9.25	3.50	3.50	0.00	0.00	4.83	4.50	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Overall L1	9.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.25 cycles. At this rate:

6% of peak load performance is reached (6.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.05 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42f340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
ADD X13, X4, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, X21, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS W15, W19, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
ADD X1, X20, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X20, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B.EQ 42f420 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f404 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f3f0 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f3dc <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W15, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f3c8 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W15, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f3b4 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W15, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f3a0 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X20, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D0, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D1, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D1, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D2, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D2, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D3, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D3, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D4, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D4, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D5, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D5, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D6, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D6, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W19, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f4a8 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W30, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W6, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 42f340 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0x90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.12]
Source file and lines	update_halo.cpp:175-176
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:175-176

Analyzed code is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:175-176.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=15
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.25 to 4.83 cycles (1.91x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	9.25	9.25	9.25	9.25	3.50	3.50	0.00	0.00	4.83	4.50	4.67	0.00	0.00
cycles	4.50	4.50	9.25	9.25	9.25	9.25	3.50	3.50	0.00	0.00	4.83	4.50	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Overall L1	9.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.25 cycles. At this rate:

6% of peak load performance is reached (6.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.05 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42f340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
ADD X13, X4, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, X21, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS W15, W19, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
ADD X1, X20, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X20, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B.EQ 42f420 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f404 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f3f0 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f3dc <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W15, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f3c8 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W15, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f3b4 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W15, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f3a0 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0xf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X20, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D0, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D1, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D1, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D2, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D2, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D3, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D3, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D4, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D4, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D5, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D5, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D6, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D6, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W19, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 42f4a8 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W30, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W6, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 42f340 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.12+0x90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code