OV - exec - Loop 399

	Loop Id: 399	Module: exec	Source: PdV.cpp:71-83 [...]	Coverage: 0.04%

0x42c884 LDP	X10, X12, [SP, #256]

0x42c888 SBFM	X1, X9, #0, #31

0x42c88c ORR	W2, WZR, W2

0x42c890 ADD	X3, X1, #1

0x42c894 WHILELO	P0.D, XZR, X2

0x42c898 LDP	X24, X21, [SP, #104]

0x42c89c LDP	X27, X0, [SP, #272]

0x42c8a0 LDP	X8, X18, [SP, #128]

0x42c8a4 LDR	X13, [X10]

0x42c8a8 LDR	X9, [X21]

0x42c8ac LDR	X6, [X0]

0x42c8b0 MADD	X14, X28, X13, XZR

0x42c8b4 LDR	X20, [X12]

0x42c8b8 MADD	X11, X28, X9, XZR

0x42c8bc LDR	X15, [X10, #16]

0x42c8c0 ADD	X16, X13, X14

0x42c8c4 ADD	X5, X14, X3

0x42c8c8 MADD	X26, X28, X6, XZR

0x42c8cc ADD	X4, X16, X3

0x42c8d0 ADD	X17, X14, X1

0x42c8d4 LDR	X10, [X12, #16]

0x42c8d8 ADD	X25, X16, X1

0x42c8dc MADD	X12, X28, X20, XZR

0x42c8e0 STR	X5, [SP, #184]

0x42c8e4 ADD	X7, X6, X26

0x42c8e8 ADD	X6, X9, X11

0x42c8ec LDR	X19, [X8]

0x42c8f0 ADD	X9, X15, X4,LSL #3

0x42c8f4 ADD	X22, X7, X1

0x42c8f8 ADD	X7, X7, X3

0x42c8fc LDR	X4, [X27]

0x42c900 ADD	X8, X20, X12

0x42c904 ADD	X14, X12, X1

0x42c908 ADD	X13, X8, X3

0x42c90c ADD	X23, X8, X1

0x42c910 ADD	X20, X10, X14,LSL #3

0x42c914 ADD	X8, X10, X13,LSL #3

0x42c918 LDR	X5, [SP, #120]

0x42c91c ADD	X16, X12, X3

0x42c920 ADD	X12, X10, X16,LSL #3

0x42c924 LDR	X30, [SP, #144]

0x42c928 ADD	X23, X10, X23,LSL #3

0x42c92c LDR	X13, [SP, #152]

0x42c930 LDR	X21, [X24]

0x42c934 ADD	X24, X15, X25,LSL #3

0x42c938 ADD	X25, X15, X17,LSL #3

0x42c93c MADD	X17, X28, X19, X1

0x42c940 LDR	X30, [X30]

0x42c944 MADD	X19, X28, X4, XZR

0x42c948 LDR	X13, [X13]

0x42c94c MADD	X14, X28, X21, XZR

0x42c950 ADD	X10, X4, X19

0x42c954 LDR	X4, [X5]

0x42c958 ADD	X16, X19, X1

0x42c95c ADD	X10, X10, X1

0x42c960 LDR	X5, [X18]

0x42c964 ADD	X18, X26, X1

0x42c968 ADD	X26, X26, X3

0x42c96c ADD	X19, X14, X3

0x42c970 ADD	X14, X14, X1

0x42c974 LDR	X27, [X27, #16]

0x42c978 MADD	X21, X28, X4, X1

0x42c97c MADD	X4, X28, X30, X1

0x42c980 MADD	X30, X28, X13, X1

0x42c984 LDR	X13, [X0, #16]

0x42c988 MADD	X5, X28, X5, X1

0x42c98c STR	X21, [SP, #192]

0x42c990 ADD	X21, X6, X1

0x42c994 ADD	X10, X27, X10,LSL #3

0x42c998 ADD	X6, X6, X3

0x42c99c ADD	X3, X11, X3

0x42c9a0 ADD	X16, X27, X16,LSL #3

0x42c9a4 ADD	X11, X11, X1

0x42c9a8 STP	X5, X4, [SP, #208]

0x42c9ac ADD	X22, X13, X22,LSL #3

0x42c9b0 ADD	X7, X13, X7,LSL #3

0x42c9b4 ADD	X18, X13, X18,LSL #3

0x42c9b8 ADD	X13, X13, X26,LSL #3

0x42c9bc LDR	X26, [SP, #160]

0x42c9c0 LDR	X5, [X26]

0x42c9c4 LDR	X0, [SP, #168]

0x42c9c8 LDR	X4, [SP, #112]

0x42c9cc MADD	X5, X28, X5, X1

0x42c9d0 LDR	X26, [SP, #120]

0x42c9d4 LDR	X0, [X0]

0x42c9d8 LDR	X27, [X4, #16]

0x42c9dc MADD	X4, X28, X0, X1

0x42c9e0 LDR	X1, [SP, #104]

0x42c9e4 ADD	X21, X27, X21,LSL #3

0x42c9e8 ADD	X6, X27, X6,LSL #3

0x42c9ec ADD	X3, X27, X3,LSL #3

0x42c9f0 LDR	X0, [X1, #16]

0x42c9f4 ADD	X11, X27, X11,LSL #3

0x42c9f8 LDR	X1, [X26, #16]

0x42c9fc STR	X0, [SP, #176]

0x42ca00 LDR	X27, [SP, #176]

0x42ca04 STR	X1, [SP, #200]

0x42ca08 LDR	X0, [SP, #184]

0x42ca0c LDR	X26, [SP, #200]

0x42ca10 ADD	X14, X27, X14,LSL #3

0x42ca14 ADD	X19, X27, X19,LSL #3

0x42ca18 LDR	X27, [SP, #128]

0x42ca1c ADD	X15, X15, X0,LSL #3

0x42ca20 LDR	X0, [SP, #136]

0x42ca24 LDR	X1, [X27, #16]

0x42ca28 LDR	X27, [X0, #16]

0x42ca2c LDR	X0, [SP, #152]

0x42ca30 STR	X1, [SP, #184]

0x42ca34 LDR	X1, [SP, #144]

0x42ca38 STR	X27, [SP, #176]

0x42ca3c LDR	X27, [X1, #16]

0x42ca40 LDR	X1, [X0, #16]

0x42ca44 LDR	X0, [SP, #192]

0x42ca48 STR	X27, [SP, #224]

0x42ca4c LDR	X27, [SP, #160]

0x42ca50 STR	X1, [SP, #232]

0x42ca54 ADD	X1, X26, X0,LSL #3

0x42ca58 LDR	X26, [SP, #184]

0x42ca5c LDR	X27, [X27, #16]

0x42ca60 LDR	X0, [SP, #208]

0x42ca64 ADD	X17, X26, X17,LSL #3

0x42ca68 STR	X27, [SP, #184]

0x42ca6c LDP	X27, X26, [SP, #168]

0x42ca70 LDR	X27, [X27, #16]

0x42ca74 ADD	X26, X26, X0,LSL #3

0x42ca78 LDR	X0, [SP, #216]

0x42ca7c STR	X27, [SP, #176]

0x42ca80 LDR	X27, [SP, #224]

0x42ca84 ADD	X27, X27, X0,LSL #3

0x42ca88 LDR	X0, [SP, #232]

0x42ca8c ADD	X30, X0, X30,LSL #3

0x42ca90 LDR	X0, [SP, #184]

0x42ca94 ADD	X5, X0, X5,LSL #3

0x42ca98 LDR	X0, [SP, #176]

0x42ca9c ADD	X4, X0, X4,LSL #3

0x42caa0 MOVZ	X0, #0

  (397) 0x42caa4 LD1D	{Z3.D}, P0/Z, [X18, X0,LSL #3]

  (397) 0x42caa8 LD1D	{Z6.D}, P0/Z, [X13, X0,LSL #3]

  (397) 0x42caac LD1D	{Z2.D}, P0/Z, [X11, X0,LSL #3]

  (397) 0x42cab0 LD1D	{Z17.D}, P0/Z, [X3, X0,LSL #3]

  (397) 0x42cab4 LD1D	{Z18.D}, P0/Z, [X16, X0,LSL #3]

  (397) 0x42cab8 LD1D	{Z20.D}, P0/Z, [X25, X0,LSL #3]

  (397) 0x42cabc LD1D	{Z22.D}, P0/Z, [X24, X0,LSL #3]

  (397) 0x42cac0 LD1D	{Z25.D}, P0/Z, [X20, X0,LSL #3]

  (397) 0x42cac4 LD1D	{Z26.D}, P0/Z, [X23, X0,LSL #3]

  (397) 0x42cac8 LD1D	{Z27.D}, P0/Z, [X14, X0,LSL #3]

  (397) 0x42cacc LD1D	{Z29.D}, P0/Z, [X22, X0,LSL #3]

  (397) 0x42cad0 LD1D	{Z31.D}, P0/Z, [X7, X0,LSL #3]

  (397) 0x42cad4 LD1D	{Z4.D}, P0/Z, [X21, X0,LSL #3]

  (397) 0x42cad8 LD1D	{Z1.D}, P0/Z, [X6, X0,LSL #3]

  (397) 0x42cadc FADD	Z7.D, Z6.D, Z3.D

  (397) 0x42cae0 FADD	Z19.D, Z17.D, Z2.D

  (397) 0x42cae4 LD1D	{Z6.D}, P0/Z, [X15, X0,LSL #3]

  (397) 0x42cae8 LD1D	{Z2.D}, P0/Z, [X10, X0,LSL #3]

  (397) 0x42caec FADD	Z21.D, Z19.D, Z7.D

  (397) 0x42caf0 FADD	Z24.D, Z22.D, Z20.D

  (397) 0x42caf4 FMUL	Z23.D, Z21.D, Z18.D

  (397) 0x42caf8 FADD	Z28.D, Z26.D, Z25.D

  (397) 0x42cafc FADD	Z0.D, Z31.D, Z29.D

  (397) 0x42cb00 FADD	Z3.D, Z1.D, Z4.D

  (397) 0x42cb04 FADD	Z30.D, Z28.D, Z24.D

  (397) 0x42cb08 FMAD	Z30.D, P1/M, Z27.D, Z23.D

  (397) 0x42cb0c LD1D	{Z31.D}, P0/Z, [X1, X0,LSL #3]

  (397) 0x42cb10 LD1D	{Z17.D}, P0/Z, [X9, X0,LSL #3]

  (397) 0x42cb14 LD1D	{Z20.D}, P0/Z, [X12, X0,LSL #3]

  (397) 0x42cb18 LD1D	{Z21.D}, P0/Z, [X8, X0,LSL #3]

  (397) 0x42cb1c LD1D	{Z22.D}, P0/Z, [X19, X0,LSL #3]

  (397) 0x42cb20 LD1D	{Z24.D}, P0/Z, [X17, X0,LSL #3]

  (397) 0x42cb24 LD1D	{Z26.D}, P0/Z, [X27, X0,LSL #3]

  (397) 0x42cb28 LD1D	{Z29.D}, P0/Z, [X26, X0,LSL #3]

  (397) 0x42cb2c FADD	Z7.D, Z3.D, Z0.D

  (397) 0x42cb30 FADD	Z19.D, Z17.D, Z6.D

  (397) 0x42cb34 LD1D	{Z0.D}, P0/Z, [X30, X0,LSL #3]

  (397) 0x42cb38 FMUL	Z18.D, Z7.D, Z2.D

  (397) 0x42cb3c MOVPRFX	Z4, Z5

  (397) 0x42cb40 FDIV	Z4.D, P1/M, Z4.D, Z31.D

  (397) 0x42cb44 FADD	Z23.D, Z21.D, Z20.D

  (397) 0x42cb48 FADD	Z27.D, Z26.D, Z24.D

  (397) 0x42cb4c FADD	Z25.D, Z23.D, Z19.D

  (397) 0x42cb50 FDIV	Z27.D, P1/M, Z27.D, Z29.D

  (397) 0x42cb54 FMAD	Z25.D, P1/M, Z22.D, Z18.D

  (397) 0x42cb58 FMUL	Z1.D, Z27.D, Z4.D

  (397) 0x42cb5c FSUB	Z28.D, Z25.D, Z30.D

  (397) 0x42cb60 FMUL	Z30.D, Z28.D, Z16.D

  (397) 0x42cb64 FADD	Z2.D, Z31.D, Z30.D

  (397) 0x42cb68 FMSB	Z30.D, P1/M, Z1.D, Z0.D

  (397) 0x42cb6c FDIV	Z31.D, P1/M, Z31.D, Z2.D

  (397) 0x42cb70 ST1D	{Z30.D}, P0, [X5, X0,LSL #3]

  (397) 0x42cb74 LD1D	{Z3.D}, P0/Z, [X26, X0,LSL #3]

  (397) 0x42cb78 FMUL	Z6.D, Z3.D, Z31.D

  (397) 0x42cb7c ST1D	{Z6.D}, P0, [X4, X0,LSL #3]

  (397) 0x42cb80 INCD	X0, ALL

  (397) 0x42cb84 WHILELO	P0.D, X0, X2

  (397) 0x42cb88 B.NE	42caa4

0x42cb8c LDR	W24, [SP, #240]

0x42cb90 ADD	X28, X28, #1

0x42cb94 ADD	W2, W28, #0

0x42cb98 CMP	W24, W2

0x42cb9c B.LE	42cbe0

0x42cba0 LDR	W8, [SP, #100]

0x42cba4 LDR	W23, [SP, #252]

0x42cba8 LDP	W9, W25, [SP, #244]

0x42cbac SUB	W7, W23, W8

0x42cbb0 CMP	W7, W25

0x42cbb4 CSEL	W2, W7, W25, #9

0x42cbb8 ADD	W23, W8, W2

0x42cbbc STR	W23, [SP, #100]

0x42cbc0 CMP	W8, W23

0x42cbc4 B.CC	42c884

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp: 71 - 83

--------------------------------------------------------------------------------

71:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.70
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	P10, P11, P12,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.1]
Source	context.h:69-69,PdV.cpp:71-71,PdV.cpp:83-83
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	23.67
CQA cycles if no scalar integer	23.67
CQA cycles if FP arith vectorized	23.67
CQA cycles if fully vectorized	3.53
Front-end cycles	18.88
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	19.50
P2 cycles	19.50
P3 cycles	19.50
P4 cycles	19.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	23.67
P10 cycles	23.67
P11 cycles	23.67
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	151.00
Nb uops	151.00
Nb loads	NA
Nb stores	12.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.35
Bytes prefetched	0.00
Bytes loaded	500.00
Bytes stored	100.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.44
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.22
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.70
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	P10, P11, P12,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.1]
Source	context.h:69-69,PdV.cpp:71-71,PdV.cpp:83-83
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	23.67
CQA cycles if no scalar integer	23.67
CQA cycles if FP arith vectorized	23.67
CQA cycles if fully vectorized	3.53
Front-end cycles	18.88
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	19.50
P2 cycles	19.50
P3 cycles	19.50
P4 cycles	19.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	23.67
P10 cycles	23.67
P11 cycles	23.67
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	151.00
Nb uops	151.00
Nb loads	NA
Nb stores	12.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.35
Bytes prefetched	0.00
Bytes loaded	500.00
Bytes stored	100.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.44
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.22
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.1]
Source file and lines	PdV.cpp:71-83
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:71-83

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 23.67 to 3.53 cycles (6.70x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 500 bytes. The binary loop is storing 100 bytes.

General properties

nb instructions	151
loop length	604
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	19.50	19.50	19.50	19.50	0.00	0.00	0.00	0.00	23.67	23.67	23.67	6.00	6.00
cycles	1.00	1.00	19.50	19.50	19.50	19.50	0.00	0.00	0.00	0.00	23.67	23.67	23.67	6.00	6.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.88
Overall L1	23.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.67 cycles. At this rate:

22% of peak load performance is reached (21.13 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.23 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42cba0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDP X10, X12, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SBFM X1, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR W2, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
WHILELO P0.D, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	3	2
LDP X24, X21, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X0, [SP, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X8, X18, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X13, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X14, X28, X13, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X20, [X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X11, X28, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X15, [X10, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X26, X28, X6, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X4, X16, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X17, X14, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X10, [X12, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X25, X16, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X12, X28, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
STR X5, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X7, X6, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X19, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X15, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X22, X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X7, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [X27]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X20, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X13, X8, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X23, X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X20, X10, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X10, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X12, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X12, X10, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X30, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X23, X10, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X13, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X24, X15, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X25, X15, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X17, X28, X19, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X30, [X30]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X19, X28, X4, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X13, [X13]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X14, X28, X21, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X10, X4, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X19, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X10, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X26, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X26, X26, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X19, X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, X14, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X27, [X27, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X21, X28, X4, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
MADD X4, X28, X30, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
MADD X30, X28, X13, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X13, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X5, X28, X5, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
STR X21, [SP, #192]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X21, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X27, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X6, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X11, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X16, X27, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X11, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X5, X4, [SP, #208]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X22, X13, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X13, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X18, X13, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X13, X13, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X26, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X5, X28, X5, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X26, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X4, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X4, X28, X0, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X1, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X21, X27, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X27, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X27, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X1, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X27, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [SP, #200]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [SP, #200]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X27, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X19, X27, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X27, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X15, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X27, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X27, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [X1, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [SP, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X27, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [SP, #232]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X26, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X26, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X27, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [SP, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X17, X26, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X27, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X27, X26, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X27, [X27, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X26, X26, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [SP, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X27, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [SP, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X27, X27, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [SP, #232]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X0, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X0, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X0, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W24, [SP, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W2, W28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W24, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 42cbe0 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x4a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W8, [SP, #100]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W23, [SP, #252]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP W9, W25, [SP, #244]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W7, W23, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W7, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W2, W7, W25, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W23, W8, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W23, [SP, #100]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W8, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 42c884 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.1]
Source file and lines	PdV.cpp:71-83
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:71-83

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 500 bytes. The binary loop is storing 100 bytes.

General properties

nb instructions	151
loop length	604
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	19.50	19.50	19.50	19.50	0.00	0.00	0.00	0.00	23.67	23.67	23.67	6.00	6.00
cycles	1.00	1.00	19.50	19.50	19.50	19.50	0.00	0.00	0.00	0.00	23.67	23.67	23.67	6.00	6.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.88
Overall L1	23.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 23.67 cycles. At this rate:

22% of peak load performance is reached (21.13 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.23 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42cba0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDP X10, X12, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SBFM X1, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR W2, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
WHILELO P0.D, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	3	2
LDP X24, X21, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X0, [SP, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X8, X18, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X13, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X14, X28, X13, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X20, [X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X11, X28, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X15, [X10, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X26, X28, X6, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X4, X16, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X17, X14, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X10, [X12, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X25, X16, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X12, X28, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
STR X5, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X7, X6, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X19, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X15, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X22, X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X7, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [X27]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X20, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X13, X8, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X23, X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X20, X10, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X10, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X12, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X12, X10, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X30, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X23, X10, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X13, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X24, X15, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X25, X15, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X17, X28, X19, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X30, [X30]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X19, X28, X4, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X13, [X13]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X14, X28, X21, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X10, X4, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X19, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X10, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X26, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X26, X26, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X19, X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, X14, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X27, [X27, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X21, X28, X4, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
MADD X4, X28, X30, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
MADD X30, X28, X13, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X13, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X5, X28, X5, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
STR X21, [SP, #192]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X21, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X27, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X6, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X11, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X16, X27, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X11, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X5, X4, [SP, #208]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X22, X13, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X13, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X18, X13, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X13, X13, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X26, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X5, X28, X5, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X26, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X4, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X4, X28, X0, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X1, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X21, X27, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X27, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X27, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X1, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X27, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [SP, #200]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [SP, #200]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X27, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X19, X27, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X27, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X15, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X27, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X27, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [X1, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [SP, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X27, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [SP, #232]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X26, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X26, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X27, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [SP, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X17, X26, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X27, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X27, X26, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X27, [X27, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X26, X26, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [SP, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X27, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [SP, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X27, X27, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [SP, #232]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X0, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X0, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X0, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W24, [SP, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W2, W28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W24, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 42cbe0 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x4a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W8, [SP, #100]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W23, [SP, #252]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP W9, W25, [SP, #244]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W7, W23, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W7, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W2, W7, W25, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W23, W8, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W23, [SP, #100]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W8, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 42c884 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code