OV - exec - Loop 397

	Loop Id: 397	Module: exec	Source: PdV.cpp:72-83	Coverage: 4.09%

0x42caa4 LD1D	{Z3.D}, P0/Z, [X18, X0,LSL #3]    [12]

0x42caa8 LD1D	{Z6.D}, P0/Z, [X13, X0,LSL #3]    [22]

0x42caac LD1D	{Z2.D}, P0/Z, [X11, X0,LSL #3]    [24]

0x42cab0 LD1D	{Z17.D}, P0/Z, [X3, X0,LSL #3]    [2]

0x42cab4 LD1D	{Z18.D}, P0/Z, [X16, X0,LSL #3]    [10]

0x42cab8 LD1D	{Z20.D}, P0/Z, [X25, X0,LSL #3]    [7]

0x42cabc LD1D	{Z22.D}, P0/Z, [X24, X0,LSL #3]    [11]

0x42cac0 LD1D	{Z25.D}, P0/Z, [X20, X0,LSL #3]    [19]

0x42cac4 LD1D	{Z26.D}, P0/Z, [X23, X0,LSL #3]    [26]

0x42cac8 LD1D	{Z27.D}, P0/Z, [X14, X0,LSL #3]    [1]

0x42cacc LD1D	{Z29.D}, P0/Z, [X22, X0,LSL #3]    [25]

0x42cad0 LD1D	{Z31.D}, P0/Z, [X7, X0,LSL #3]    [3]

0x42cad4 LD1D	{Z4.D}, P0/Z, [X21, X0,LSL #3]    [8]

0x42cad8 LD1D	{Z1.D}, P0/Z, [X6, X0,LSL #3]    [14]

0x42cadc FADD	Z7.D, Z6.D, Z3.D

0x42cae0 FADD	Z19.D, Z17.D, Z2.D

0x42cae4 LD1D	{Z6.D}, P0/Z, [X15, X0,LSL #3]    [20]

0x42cae8 LD1D	{Z2.D}, P0/Z, [X10, X0,LSL #3]    [18]

0x42caec FADD	Z21.D, Z19.D, Z7.D

0x42caf0 FADD	Z24.D, Z22.D, Z20.D

0x42caf4 FMUL	Z23.D, Z21.D, Z18.D

0x42caf8 FADD	Z28.D, Z26.D, Z25.D

0x42cafc FADD	Z0.D, Z31.D, Z29.D

0x42cb00 FADD	Z3.D, Z1.D, Z4.D

0x42cb04 FADD	Z30.D, Z28.D, Z24.D

0x42cb08 FMAD	Z30.D, P1/M, Z27.D, Z23.D

0x42cb0c LD1D	{Z31.D}, P0/Z, [X1, X0,LSL #3]    [9]

0x42cb10 LD1D	{Z17.D}, P0/Z, [X9, X0,LSL #3]    [6]

0x42cb14 LD1D	{Z20.D}, P0/Z, [X12, X0,LSL #3]    [23]

0x42cb18 LD1D	{Z21.D}, P0/Z, [X8, X0,LSL #3]    [4]

0x42cb1c LD1D	{Z22.D}, P0/Z, [X19, X0,LSL #3]    [17]

0x42cb20 LD1D	{Z24.D}, P0/Z, [X17, X0,LSL #3]    [13]

0x42cb24 LD1D	{Z26.D}, P0/Z, [X27, X0,LSL #3]    [15]

0x42cb28 LD1D	{Z29.D}, P0/Z, [X26, X0,LSL #3]    [16]

0x42cb2c FADD	Z7.D, Z3.D, Z0.D

0x42cb30 FADD	Z19.D, Z17.D, Z6.D

0x42cb34 LD1D	{Z0.D}, P0/Z, [X30, X0,LSL #3]    [5]

0x42cb38 FMUL	Z18.D, Z7.D, Z2.D

0x42cb3c MOVPRFX	Z4, Z5

0x42cb40 FDIV	Z4.D, P1/M, Z4.D, Z31.D

0x42cb44 FADD	Z23.D, Z21.D, Z20.D

0x42cb48 FADD	Z27.D, Z26.D, Z24.D

0x42cb4c FADD	Z25.D, Z23.D, Z19.D

0x42cb50 FDIV	Z27.D, P1/M, Z27.D, Z29.D

0x42cb54 FMAD	Z25.D, P1/M, Z22.D, Z18.D

0x42cb58 FMUL	Z1.D, Z27.D, Z4.D

0x42cb5c FSUB	Z28.D, Z25.D, Z30.D

0x42cb60 FMUL	Z30.D, Z28.D, Z16.D

0x42cb64 FADD	Z2.D, Z31.D, Z30.D

0x42cb68 FMSB	Z30.D, P1/M, Z1.D, Z0.D

0x42cb6c FDIV	Z31.D, P1/M, Z31.D, Z2.D

0x42cb70 ST1D	{Z30.D}, P0, [X5, X0,LSL #3]    [27]

0x42cb74 LD1D	{Z3.D}, P0/Z, [X26, X0,LSL #3]    [16]

0x42cb78 FMUL	Z6.D, Z3.D, Z31.D

0x42cb7c ST1D	{Z6.D}, P0, [X4, X0,LSL #3]    [21]

0x42cb80 INCD	X0, ALL

0x42cb84 WHILELO	P0.D, X0, X2

0x42cb88 B.NE	42caa4

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp: 72 - 83

--------------------------------------------------------------------------------

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P10, P11,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.1]
Source	PdV.cpp:72-83
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	16
CQA cycles	14.00
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	14.00
Front-end cycles	7.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.00
P2 cycles	0.00
P3 cycles	2.00
P4 cycles	0.00
P5 cycles	13.50
P6 cycles	13.50
P7 cycles	11.50
P8 cycles	11.50
P9 cycles	14.00
P10 cycles	14.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	3.00 - 1.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	58.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	8.29
Nb FLOP add-sub	60.00
Nb FLOP mul	20.00
Nb FLOP fma	12.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	832.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	98.18
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P10, P11,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.1]
Source	PdV.cpp:72-83
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	16
CQA cycles	14.00
CQA cycles if no scalar integer	14.00
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	14.00
Front-end cycles	7.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.00
P2 cycles	0.00
P3 cycles	2.00
P4 cycles	0.00
P5 cycles	13.50
P6 cycles	13.50
P7 cycles	11.50
P8 cycles	11.50
P9 cycles	14.00
P10 cycles	14.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	3.00 - 1.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	58.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	8.29
Nb FLOP add-sub	60.00
Nb FLOP mul	20.00
Nb FLOP fma	12.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	832.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	98.18
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.1]
Source file and lines	PdV.cpp:72-83
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:72-83.

The related source loop is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

98% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 116 FP arithmetical operations:

72: addition or subtraction (12 inside FMA instructions)
32: multiply (12 inside FMA instructions)
12: divide

The binary loop is loading 832 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	58
loop length	232
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.00	0.00	2.00	0.00	13.50	13.50	1.00	1.00	14.00	14.00	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	2.00	0.00	13.50	13.50	11.50	11.50	14.00	14.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	3.00-1.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	7.25
Data deps.	2.00
Overall L1	14.00

Vectorization ratios

INT

all	96%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

61% of peak load performance is reached (59.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42caa4

Instruction	Nb FU	P0	P1	P4	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z3.D}, P0/Z, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P0/Z, [X13, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P0/Z, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P0/Z, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z18.D}, P0/Z, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P0/Z, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P0/Z, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P0/Z, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z27.D}, P0/Z, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z29.D}, P0/Z, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z4.D}, P0/Z, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P0/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z7.D, Z6.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z19.D, Z17.D, Z2.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z6.D}, P0/Z, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P0/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z21.D, Z19.D, Z7.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z24.D, Z22.D, Z20.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, Z21.D, Z18.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z28.D, Z26.D, Z25.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z0.D, Z31.D, Z29.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z3.D, Z1.D, Z4.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z30.D, Z28.D, Z24.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z30.D, P1/M, Z27.D, Z23.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z31.D}, P0/Z, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P0/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z21.D}, P0/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P0/Z, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P0/Z, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P0/Z, [X27, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z29.D}, P0/Z, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z7.D, Z3.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z19.D, Z17.D, Z6.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z0.D}, P0/Z, [X30, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z18.D, Z7.D, Z2.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z4, Z5	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z4.D, P1/M, Z4.D, Z31.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z23.D, Z21.D, Z20.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z27.D, Z26.D, Z24.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z25.D, Z23.D, Z19.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z27.D, P1/M, Z27.D, Z29.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMAD Z25.D, P1/M, Z22.D, Z18.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z1.D, Z27.D, Z4.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z28.D, Z25.D, Z30.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z30.D, Z28.D, Z16.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z2.D, Z31.D, Z30.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMSB Z30.D, P1/M, Z1.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIV Z31.D, P1/M, Z31.D, Z2.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
ST1D {Z30.D}, P0, [X5, X0,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z3.D}, P0/Z, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z6.D, Z3.D, Z31.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z6.D}, P0, [X4, X0,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
INCD X0, ALL	1	0	0	1	0	0	0	0	0	0	2	1
WHILELO P0.D, X0, X2	1	0	0	1	0	0	0	0	0	0	3	2
B.NE 42caa4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x364>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.1]
Source file and lines	PdV.cpp:72-83
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/PdV.cpp:72-83.

The related source loop is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

98% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 116 FP arithmetical operations:

72: addition or subtraction (12 inside FMA instructions)
32: multiply (12 inside FMA instructions)
12: divide

The binary loop is loading 832 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	58
loop length	232
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.00	0.00	2.00	0.00	13.50	13.50	1.00	1.00	14.00	14.00	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	2.00	0.00	13.50	13.50	11.50	11.50	14.00	14.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	3.00-1.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	7.25
Data deps.	2.00
Overall L1	14.00

Vectorization ratios

INT

all	96%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	98%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

61% of peak load performance is reached (59.43 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42caa4

Instruction	Nb FU	P0	P1	P4	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z3.D}, P0/Z, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P0/Z, [X13, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P0/Z, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P0/Z, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z18.D}, P0/Z, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P0/Z, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P0/Z, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P0/Z, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z27.D}, P0/Z, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z29.D}, P0/Z, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P0/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z4.D}, P0/Z, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P0/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z7.D, Z6.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z19.D, Z17.D, Z2.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z6.D}, P0/Z, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P0/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z21.D, Z19.D, Z7.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z24.D, Z22.D, Z20.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, Z21.D, Z18.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z28.D, Z26.D, Z25.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z0.D, Z31.D, Z29.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z3.D, Z1.D, Z4.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z30.D, Z28.D, Z24.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMAD Z30.D, P1/M, Z27.D, Z23.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z31.D}, P0/Z, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P0/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z21.D}, P0/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P0/Z, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P0/Z, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P0/Z, [X27, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z29.D}, P0/Z, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z7.D, Z3.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z19.D, Z17.D, Z6.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z0.D}, P0/Z, [X30, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z18.D, Z7.D, Z2.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z4, Z5	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z4.D, P1/M, Z4.D, Z31.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z23.D, Z21.D, Z20.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z27.D, Z26.D, Z24.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z25.D, Z23.D, Z19.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z27.D, P1/M, Z27.D, Z29.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMAD Z25.D, P1/M, Z22.D, Z18.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z1.D, Z27.D, Z4.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z28.D, Z25.D, Z30.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z30.D, Z28.D, Z16.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z2.D, Z31.D, Z30.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMSB Z30.D, P1/M, Z1.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIV Z31.D, P1/M, Z31.D, Z2.D	1	0	0	0	1	0	0	0	0	0	7-15	1-0.50
ST1D {Z30.D}, P0, [X5, X0,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z3.D}, P0/Z, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z6.D, Z3.D, Z31.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z6.D}, P0, [X4, X0,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
INCD X0, ALL	1	0	0	1	0	0	0	0	0	0	2	1
WHILELO P0.D, X0, X2	1	0	0	1	0	0	0	0	0	0	3	2
B.NE 42caa4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x364>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code