OV - exec - Loop 326

	Loop Id: 326	Module: exec	Source: generate_chunk.cpp:88-116 [...]	Coverage: 0.02%

0x426ebc ADD	X0, X0, #1

0x426ec0 LDR	D3, [X6]    [1]

0x426ec4 LDR	D1, [X7]    [2]

0x426ec8 CMP	W2, #1

0x426ecc B.NE	426ea0

0x426ed0 LDR	X17, [X4, #600]    [29]

0x426ed4 ADD	X16, X17, X1,LSL #3

0x426ed8 LDR	D16, [X16, #8]    [11]

0x426edc FCMPE	D16, D1

0x426ee0 B.MI	426eb0

0x426ee4 LDR	X15, [X21, #8]    [15]

0x426ee8 LDR	D17, [X17, X1,LSL #3]    [24]

0x426eec LDR	D18, [X15, X5]    [21]

0x426ef0 FCMPE	D17, D18

0x426ef4 B.GE	426eb0

0x426ef8 LDR	X20, [X4, #632]    [29]

0x426efc LDR	D19, [X20, X19]    [26]

0x426f00 FCMPE	D19, D3

0x426f04 B.MI	426eb0

0x426f08 LDR	X18, [SP, #152]    [8]

0x426f0c LDR	D20, [X20, X13]    [17]

0x426f10 LDR	X28, [X18, #8]    [19]

0x426f14 LDR	D21, [X28, X5]    [27]

0x426f18 FCMPE	D20, D21

0x426f1c B.GE	426eb0

0x426f20 LDR	X11, [X22, #8]    [16]

0x426f24 LDP	X28, X15, [SP, #120]    [8]

0x426f28 LDR	X14, [X4, #48]    [29]

0x426f2c LDR	D22, [X11, X5]    [12]

0x426f30 LDR	X17, [X4]    [29]

0x426f34 MADD	X12, X9, X14, X1

0x426f38 LDR	X20, [X15, #8]    [6]

0x426f3c LDR	X26, [X4, #64]    [29]

0x426f40 MADD	X11, X9, X17, X1

0x426f44 LDR	X16, [SP, #136]    [8]

0x426f48 LDR	X14, [X4, #16]    [29]

0x426f4c LDR	X15, [SP, #144]    [8]

0x426f50 LDR	X17, [X16, #8]    [14]

0x426f54 STR	D22, [X26, X12,LSL #3]    [13]

0x426f58 LDR	D23, [X20, X5]    [18]

0x426f5c LDR	X18, [X4, #168]    [29]

0x426f60 LDR	X15, [X15, #8]    [28]

0x426f64 LDR	X16, [X4, #184]    [29]

0x426f68 STR	D23, [X14, X11,LSL #3]    [10]

0x426f6c MADD	X26, X18, X9, XZR

0x426f70 LDR	D24, [X17, X5]    [4]

0x426f74 MADD	X12, X28, X18, XZR

0x426f78 LDR	X11, [X4, #216]    [29]

0x426f7c ADD	X18, X26, X1

0x426f80 ADD	X20, X0, X26

0x426f84 ADD	X26, X12, X1

0x426f88 ADD	X12, X0, X12

0x426f8c LDR	X14, [X4, #232]    [29]

0x426f90 STR	D24, [X16, X18,LSL #3]    [30]

0x426f94 LDR	D25, [X15, X5]    [25]

0x426f98 MADD	X18, X11, X9, XZR

0x426f9c MADD	X11, X28, X11, XZR

0x426fa0 ADD	X28, X18, X1

0x426fa4 ADD	X18, X0, X18

0x426fa8 ADD	X1, X11, X1

0x426fac ADD	X11, X0, X11

0x426fb0 STR	D25, [X14, X28,LSL #3]    [20]

0x426fb4 LDR	D26, [X17, X5]    [4]

0x426fb8 STR	D26, [X16, X20,LSL #3]    [23]

0x426fbc LDR	D27, [X15, X5]    [25]

0x426fc0 STR	D27, [X14, X18,LSL #3]    [22]

0x426fc4 LDR	D28, [X17, X5]    [4]

0x426fc8 STR	D28, [X16, X26,LSL #3]    [9]

0x426fcc LDR	D29, [X15, X5]    [25]

0x426fd0 STR	D29, [X14, X1,LSL #3]    [7]

0x426fd4 ORR	X1, XZR, X0

0x426fd8 LDR	D30, [X17, X5]    [4]

0x426fdc STR	D30, [X16, X12,LSL #3]    [3]

0x426fe0 LDR	D31, [X15, X5]    [25]

0x426fe4 STR	D31, [X14, X11,LSL #3]    [5]

0x426fe8 CMP	X3, X0

0x426fec B.NE	426ebc

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp: 88 - 116

--------------------------------------------------------------------------------

88:         double x_cent = state_xmin[state];

89:         double y_cent = state_ymin[state];

90:         if (state_geometry[state] == g_rect) {

91:           if (field.vertexx[i + 1] >= state_xmin[state] && field.vertexx[i] < state_xmax[state]) {

92:             if (field.vertexy[j + 1] >= state_ymin[state] && field.vertexy[j] < state_ymax[state]) {

93:               field.energy0(i, j) = state_energy[state];

94:               field.density0(i, j) = state_density[state];

95:               for (int kt = j; kt <= j + 1; ++kt) {

96:                 for (int jt = i; jt <= i + 1; ++jt) {

97:                   field.xvel0(jt, kt) = state_xvel[state];

98:                   field.yvel0(jt, kt) = state_yvel[state];

[...]

116:         } else if (state_geometry[state] == g_point) {

Path /

Metric	Value
CQA speedup if no scalar integer	1.71
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.05
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.66
Bottlenecks	P10, P11, P12,
Function	generate_chunk(int, global_variables&) [clone ._omp_fn.1]
Source	context.h:46-46,context.h:69-69,generate_chunk.cpp:88-98,generate_chunk.cpp:116-116
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	9.33
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	3.17
Front-end cycles	9.63
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	4.50
P2 cycles	4.25
P3 cycles	6.00
P4 cycles	4.25
P5 cycles	7.00
P6 cycles	7.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	16.00
P10 cycles	16.00
P11 cycles	16.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	77.00
Nb uops	77.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.50
Bytes prefetched	0.00
Bytes loaded	312.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.57
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.71
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.05
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.66
Bottlenecks	P10, P11, P12,
Function	generate_chunk(int, global_variables&) [clone ._omp_fn.1]
Source	context.h:46-46,context.h:69-69,generate_chunk.cpp:88-98,generate_chunk.cpp:116-116
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	9.33
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	3.17
Front-end cycles	9.63
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	4.50
P2 cycles	4.25
P3 cycles	6.00
P4 cycles	4.25
P5 cycles	7.00
P6 cycles	7.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	16.00
P10 cycles	16.00
P11 cycles	16.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	77.00
Nb uops	77.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.50
Bytes prefetched	0.00
Bytes loaded	312.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.57
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	generate_chunk(int, global_variables&) [clone ._omp_fn.1]
Source file and lines	generate_chunk.cpp:88-116
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp:88-98,116

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.00 to 9.33 cycles (1.71x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 16.00 to 3.17 cycles (5.05x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 312 bytes. The binary loop is storing 80 bytes.

General properties

nb instructions	77
loop length	308
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	4.50	4.25	6.00	4.25	7.00	7.00	0.00	0.00	16.00	16.00	16.00	0.00	0.00
cycles	3.00	3.00	4.50	4.25	6.00	4.25	7.00	7.00	0.00	0.00	16.00	16.00	16.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.63
Overall L1	16.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

20% of peak load performance is reached (19.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (5.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 426ec0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D3, [X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D1, [X7]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMP W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 426ea0 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X4, #600]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X16, X17, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D16, [X16, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D16, D1	1	0	0	0	0	0	0	1	0	0	0	0	2	1
B.MI 426eb0 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X21, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D17, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D18, [X15, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D17, D18	1	0	0	0	0	0	0	1	0	0	0	0	2	1
B.GE 426eb0 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X20, [X4, #632]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D19, [X20, X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D19, D3	1	0	0	0	0	0	0	1	0	0	0	0	2	1
B.MI 426eb0 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [SP, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D20, [X20, X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X28, [X18, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D21, [X28, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D20, D21	1	0	0	0	0	0	0	1	0	0	0	0	2	1
B.GE 426eb0 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X22, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDP X28, X15, [SP, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDR X14, [X4, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D22, [X11, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X17, [X4]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X12, X9, X14, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X20, [X15, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X26, [X4, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X11, X9, X17, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X16, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X14, [X4, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X16, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
STR D22, [X26, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D23, [X20, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X18, [X4, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [X15, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X16, [X4, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
STR D23, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
MADD X26, X18, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR D24, [X17, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MADD X12, X28, X18, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X11, [X4, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X18, X26, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X20, X0, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X26, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X12, X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X14, [X4, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
STR D24, [X16, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D25, [X15, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MADD X18, X11, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
MADD X11, X28, X11, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X28, X18, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X18, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X11, X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D25, [X14, X28,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D26, [X17, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D26, [X16, X20,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D27, [X15, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D27, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D28, [X17, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D28, [X16, X26,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D29, [X15, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D29, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D30, [X17, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D30, [X16, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D31, [X15, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D31, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 426ebc <_Z14generate_chunkiR16global_variables._omp_fn.1+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	generate_chunk(int, global_variables&) [clone ._omp_fn.1]
Source file and lines	generate_chunk.cpp:88-116
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/generate_chunk.cpp:88-98,116

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.00 to 9.33 cycles (1.71x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 312 bytes. The binary loop is storing 80 bytes.

General properties

nb instructions	77
loop length	308
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	4.50	4.25	6.00	4.25	7.00	7.00	0.00	0.00	16.00	16.00	16.00	0.00	0.00
cycles	3.00	3.00	4.50	4.25	6.00	4.25	7.00	7.00	0.00	0.00	16.00	16.00	16.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.63
Overall L1	16.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

20% of peak load performance is reached (19.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (5.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 426ec0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D3, [X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D1, [X7]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CMP W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 426ea0 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X4, #600]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X16, X17, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D16, [X16, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D16, D1	1	0	0	0	0	0	0	1	0	0	0	0	2	1
B.MI 426eb0 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X21, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D17, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D18, [X15, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D17, D18	1	0	0	0	0	0	0	1	0	0	0	0	2	1
B.GE 426eb0 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X20, [X4, #632]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D19, [X20, X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D19, D3	1	0	0	0	0	0	0	1	0	0	0	0	2	1
B.MI 426eb0 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [SP, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D20, [X20, X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X28, [X18, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D21, [X28, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D20, D21	1	0	0	0	0	0	0	1	0	0	0	0	2	1
B.GE 426eb0 <_Z14generate_chunkiR16global_variables._omp_fn.1+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X22, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDP X28, X15, [SP, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDR X14, [X4, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D22, [X11, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X17, [X4]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X12, X9, X14, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X20, [X15, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X26, [X4, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X11, X9, X17, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X16, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X14, [X4, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X17, [X16, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
STR D22, [X26, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D23, [X20, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X18, [X4, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X15, [X15, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X16, [X4, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
STR D23, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
MADD X26, X18, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR D24, [X17, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MADD X12, X28, X18, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X11, [X4, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X18, X26, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X20, X0, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X26, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X12, X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X14, [X4, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
STR D24, [X16, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D25, [X15, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MADD X18, X11, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
MADD X11, X28, X11, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X28, X18, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X18, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X11, X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D25, [X14, X28,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D26, [X17, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D26, [X16, X20,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D27, [X15, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D27, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D28, [X17, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D28, [X16, X26,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D29, [X15, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D29, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ORR X1, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D30, [X17, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D30, [X16, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D31, [X15, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D31, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 426ebc <_Z14generate_chunkiR16global_variables._omp_fn.1+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code