OV - exec - Loop 308

	Loop Id: 308	Module: exec	Source: context.h:69-69 [...]	Coverage: 0.7%

0x4263cc SDIV	W25, W5, W22

0x4263d0 ADD	W26, W25, W11

0x4263d4 MSUB	W27, W25, W22, W5

0x4263d8 ADD	W5, W5, #1

0x4263dc SBFM	X3, X26, #0, #31

0x4263e0 ADD	W30, W26, #1

0x4263e4 SBFM	X24, X30, #0, #31

0x4263e8 MADD	X2, X8, X3, XZR

0x4263ec ADD	W1, W27, W10

0x4263f0 SBFM	X20, X1, #0, #31

0x4263f4 MADD	X23, X9, X3, XZR

0x4263f8 ADD	W4, W1, #1

0x4263fc SBFM	X27, X4, #0, #31

0x426400 MADD	X30, X9, X24, XZR

0x426404 ADD	X25, X20, X2

0x426408 ADD	X4, X2, X27

0x42640c MADD	X2, X8, X24, XZR

0x426410 ADD	X26, X20, X23

0x426414 ADD	X23, X23, X27

0x426418 MADD	X24, X13, X3, X20

0x42641c LDR	D2, [X0, X25,LSL #3]    [7]

0x426420 ADD	X25, X20, X30

0x426424 ADD	X30, X27, X30

0x426428 ADD	X1, X27, X2

0x42642c ADD	X2, X20, X2

0x426430 MADD	X27, X19, X3, X20

0x426434 LDR	D0, [X6, X26,LSL #3]    [9]

0x426438 MADD	X26, X17, X3, X20

0x42643c MADD	X3, X15, X3, X20

0x426440 LDR	D1, [X6, X23,LSL #3]    [10]

0x426444 FMUL	D6, D2, D2

0x426448 LDR	D5, [X0, X4,LSL #3]    [6]

0x42644c LDR	D4, [X6, X25,LSL #3]    [5]

0x426450 LDR	D3, [X0, X2,LSL #3]    [2]

0x426454 FMADD	D16, D0, D0, D6

0x426458 LDR	D7, [X12, X24,LSL #3]    [8]

0x42645c LDR	D18, [X18, X27,LSL #3]    [12]

0x426460 FMADD	D19, D1, D1, D16

0x426464 LDR	D20, [X6, X30,LSL #3]    [4]

0x426468 LDR	D21, [X0, X1,LSL #3]    [11]

0x42646c FADD	D8, D8, D7

0x426470 FMUL	D22, D7, D18

0x426474 LDR	D23, [X16, X26,LSL #3]    [1]

0x426478 FMADD	D24, D5, D5, D19

0x42647c LDR	D25, [X14, X3,LSL #3]    [3]

0x426480 FMADD	D26, D4, D4, D24

0x426484 FMUL	D27, D22, D17

0x426488 FMADD	D11, D22, D23, D11

0x42648c FADD	D12, D12, D22

0x426490 FMADD	D9, D7, D25, D9

0x426494 FMADD	D28, D3, D3, D26

0x426498 FMADD	D29, D20, D20, D28

0x42649c FMADD	D30, D21, D21, D29

0x4264a0 FMADD	D10, D27, D30, D10

0x4264a4 CMP	W7, W5

0x4264a8 B.NE	4263cc

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/field_summary.cpp: 77 - 91

--------------------------------------------------------------------------------

77:       const int j = xmin + 1 + idx % (xmax - xmin + 1);

78:       const int k = ymin + 1 + idx / (xmax - xmin + 1);

79:       double vsqrd = 0.0;

80:       for (int kv = k; kv <= k + 1; ++kv) {

81:         for (int jv = j; jv <= j + 1; ++jv) {

82:           vsqrd += 0.25 * (field.xvel0(jv, kv) * field.xvel0(jv, kv) + field.yvel0(jv, kv) * field.yvel0(jv, kv));

83:         }

84:       }

85:       double cell_vol = field.volume(j, k);

86:       double cell_mass = cell_vol * field.density0(j, k);

87:       vol += cell_vol;

88:       mass += cell_mass;

89:       ie += cell_mass * field.energy0(j, k);

90:       ke += cell_mass * 0.5 * vsqrd;

91:       press += cell_vol * field.pressure(j, k);

Path /

Metric	Value
CQA speedup if no scalar integer	2.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43
Bottlenecks	P4,
Function	field_summary(global_variables&, parallel_&) [clone ._omp_fn.0]
Source	context.h:69-69,field_summary.cpp:77-91
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	10.00
CQA cycles if fully vectorized	2.50
Front-end cycles	7.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	6.00
P2 cycles	6.00
P3 cycles	10.00
P4 cycles	6.00
P5 cycles	3.75
P6 cycles	3.75
P7 cycles	3.75
P8 cycles	3.75
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.00
Nb uops	56.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.50
Nb FLOP add-sub	2.00
Nb FLOP mul	3.00
Nb FLOP fma	10.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.60
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	2.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43
Bottlenecks	P4,
Function	field_summary(global_variables&, parallel_&) [clone ._omp_fn.0]
Source	context.h:69-69,field_summary.cpp:77-91
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	10.00
CQA cycles if fully vectorized	2.50
Front-end cycles	7.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	6.00
P2 cycles	6.00
P3 cycles	10.00
P4 cycles	6.00
P5 cycles	3.75
P6 cycles	3.75
P7 cycles	3.75
P8 cycles	3.75
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.00
Nb uops	56.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.50
Nb FLOP add-sub	2.00
Nb FLOP mul	3.00
Nb FLOP fma	10.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.60
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	field_summary(global_variables&, parallel_&) [clone ._omp_fn.0]
Source file and lines	context.h:69-69
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/field_summary.cpp:77-91

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.00 to 4.00 cycles (2.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 10.00 to 2.50 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 10 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

12: addition or subtraction (10 inside FMA instructions)
13: multiply (10 inside FMA instructions)

The binary loop is loading 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	6.00	6.00	10.00	6.00	3.75	3.75	3.75	3.75	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	6.00	6.00	10.00	6.00	3.75	3.75	3.75	3.75	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	7.00
Data deps.	2.00
Overall L1	10.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.00 cycles. At this rate:

10% of peak load performance is reached (9.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4263cc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
SDIV W25, W5, W22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	1-0.50
ADD W26, W25, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MSUB W27, W25, W22, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X3, X26, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W30, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X24, X30, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X2, X8, X3, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD W1, W27, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X20, X1, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X23, X9, X3, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD W4, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X27, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X30, X9, X24, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X25, X20, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X4, X2, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X2, X8, X24, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X26, X20, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X23, X23, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X24, X13, X3, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D2, [X0, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X25, X20, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X30, X27, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X1, X27, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X2, X20, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X27, X19, X3, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D0, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MADD X26, X17, X3, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X3, X15, X3, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D1, [X6, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D6, D2, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D5, [X0, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D4, [X6, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D3, [X0, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D16, D0, D0, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D7, [X12, X24,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D18, [X18, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D19, D1, D1, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D20, [X6, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D21, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D8, D8, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D22, D7, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D23, [X16, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D24, D5, D5, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D25, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D26, D4, D4, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D27, D22, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D11, D22, D23, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FADD D12, D12, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D9, D7, D25, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D28, D3, D3, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D29, D20, D20, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D30, D21, D21, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D10, D27, D30, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
CMP W7, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4263cc <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	field_summary(global_variables&, parallel_&) [clone ._omp_fn.0]
Source file and lines	context.h:69-69
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/field_summary.cpp:77-91

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.00 to 4.00 cycles (2.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 10 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

12: addition or subtraction (10 inside FMA instructions)
13: multiply (10 inside FMA instructions)

The binary loop is loading 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	56
loop length	224
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	6.00	6.00	10.00	6.00	3.75	3.75	3.75	3.75	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	6.00	6.00	10.00	6.00	3.75	3.75	3.75	3.75	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	7.00
Data deps.	2.00
Overall L1	10.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.00 cycles. At this rate:

10% of peak load performance is reached (9.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4263cc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
SDIV W25, W5, W22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	1-0.50
ADD W26, W25, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MSUB W27, W25, W22, W5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X3, X26, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W30, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X24, X30, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X2, X8, X3, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD W1, W27, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X20, X1, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X23, X9, X3, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD W4, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X27, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X30, X9, X24, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X25, X20, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X4, X2, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X2, X8, X24, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X26, X20, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X23, X23, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X24, X13, X3, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D2, [X0, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X25, X20, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X30, X27, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X1, X27, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X2, X20, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X27, X19, X3, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D0, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MADD X26, X17, X3, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X3, X15, X3, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D1, [X6, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D6, D2, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D5, [X0, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D4, [X6, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D3, [X0, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D16, D0, D0, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D7, [X12, X24,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D18, [X18, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D19, D1, D1, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D20, [X6, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D21, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D8, D8, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D22, D7, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D23, [X16, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D24, D5, D5, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D25, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D26, D4, D4, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D27, D22, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D11, D22, D23, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FADD D12, D12, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D9, D7, D25, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D28, D3, D3, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D29, D20, D20, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D30, D21, D21, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D10, D27, D30, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
CMP W7, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 4263cc <_Z13field_summaryR16global_variablesR9parallel_._omp_fn.0+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code