OV - exec - Loop 296

	Loop Id: 296	Module: exec	Source: calc_dt.cpp:52-75 [...]	Coverage: 3.29%

0x424534 LDR	X28, [X23]    [16]

0x424538 SUB	W6, W5, #1

0x42453c SBFM	X3, X2, #0, #31

0x424540 ADD	X4, X3, #1

0x424544 ADD	W2, W2, #1

0x424548 LDR	X8, [X18]    [27]

0x42454c ADD	X7, X6, X4

0x424550 SBFM	X1, X2, #0, #31

0x424554 LDR	X9, [X21]    [13]

0x424558 MADD	X6, X0, X28, XZR

0x42455c STR	X1, [SP, #144]    [7]

0x424560 LDR	X12, [X22]    [29]

0x424564 UBFM	X2, X8, #61, #60

0x424568 LDR	X5, [X23, #16]    [16]

0x42456c MADD	X11, X0, X9, XZR

0x424570 LDR	X8, [X24]    [18]

0x424574 MADD	X13, X0, X12, XZR

0x424578 LDR	X10, [X21, #16]    [13]

0x42457c ADD	X12, X5, X6,LSL #3

0x424580 LDR	X16, [X22, #16]    [29]

0x424584 LDR	X5, [X26]    [23]

0x424588 ADD	X14, X10, X11,LSL #3

0x42458c LDR	X9, [X24, #16]    [18]

0x424590 MADD	X10, X0, X8, XZR

0x424594 ADD	X13, X16, X13,LSL #3

0x424598 LDR	X16, [X25]    [21]

0x42459c MADD	X6, X0, X5, XZR

0x4245a0 LDR	X8, [X26, #16]    [23]

0x4245a4 ADD	X11, X9, X10,LSL #3

0x4245a8 LDR	X9, [X30]    [10]

0x4245ac UBFM	X10, X16, #61, #60

0x4245b0 LDR	X28, [X25, #16]    [21]

0x4245b4 ADD	X6, X8, X6,LSL #3

0x4245b8 LDR	X16, [X18, #16]    [27]

0x4245bc UBFM	X5, X9, #61, #60

0x4245c0 LDR	X8, [X30, #16]    [10]

0x4245c4 LDR	X1, [X27, #8]    [24]

0x4245c8 MADD	X9, X0, X5, X8

0x4245cc MADD	X5, X15, X5, X8

0x4245d0 MADD	X8, X0, X2, X16

0x4245d4 LDR	D17, [X1, X0,LSL #3]    [14]

0x4245d8 MADD	X2, X15, X2, X16

0x4245dc MADD	X16, X10, X0, X28

0x4245e0 LDR	X1, [SP, #144]    [7]

0x4245e4 MADD	X10, X15, X10, X28

0x4245e8 LDR	X28, [SP, #136]    [7]

0x4245ec LDR	X28, [X28, #8]    [11]

0x4245f0 FMINNM	D22, D1, D3

0x4245f4 LDR	D20, [X2, X3,LSL #3]    [20]

0x4245f8 LDR	D2, [X9, X1,LSL #3]    [8]

0x4245fc LDR	D0, [X5, X1,LSL #3]    [22]

0x424600 LDR	D1, [X2, X1,LSL #3]    [15]

0x424604 LDR	D24, [X10, X3,LSL #3]    [19]

0x424608 FADD	D21, D2, D0

0x42460c LDR	D27, [X9, X3,LSL #3]    [12]

0x424610 FADD	D26, D20, D1

0x424614 LDR	D19, [X5, X3,LSL #3]    [25]

0x424618 LDR	D23, [X6, X1,LSL #3]    [28]

0x42461c LDR	D25, [X6, X3,LSL #3]    [2]

0x424620 FMUL	D29, D26, D24

0x424624 FADD	D31, D27, D19

0x424628 LDR	D30, [X8, X3,LSL #3]    [6]

0x42462c FMUL	D28, D21, D23

0x424630 LDR	D11, [X8, X1,LSL #3]    [5]

0x424634 LDR	D21, [X16, X3,LSL #3]    [17]

0x424638 FMUL	D1, D31, D25

0x42463c LDR	D2, [X13, X3,LSL #3]    [4]

0x424640 FABS	D26, D29

0x424644 FADD	D23, D28, D29

0x424648 FADD	D0, D30, D11

0x42464c LDR	D24, [X11, X3,LSL #3]    [26]

0x424650 FABS	D10, D28

0x424654 LDR	D28, [X12, X3,LSL #3]    [3]

0x424658 FADD	D30, D2, D2

0x42465c LDR	D27, [X28, X3,LSL #3]    [9]

0x424660 FMINNM	D25, D17, D27

0x424664 FMUL	D11, D25, D8

0x424668 FSUB	D19, D23, S1

0x42466c FMUL	D31, D0, D21

0x424670 LDR	D20, [X14, X3,LSL #3]    [1]

0x424674 FMUL	D27, D24, D4

0x424678 FMUL	D23, D6, D24

0x42467c ORR	X3, XZR, X4

0x424680 FMUL	D29, D5, D24

0x424684 FABS	D21, D1

0x424688 FMAXNM	D10, D21, D10

0x42468c FMAXNM	D1, D10, D27

0x424690 FDIV	D28, D30, D28

0x424694 FSUB	D2, D19, S31

0x424698 FABS	D0, D31

0x42469c FMAXNM	D26, D0, D26

0x4246a0 FMAXNM	D30, D26, D27

0x4246a4 FDIV	D19, D23, D1

0x4246a8 FMUL	D31, D2, D16

0x4246ac FDIV	D25, D29, D30

0x4246b0 FMINNM	D21, D19, D25

0x4246b4 FMINNM	D22, D22, D21

0x4246b8 FMADD	D20, D20, D20, D28

0x4246bc FDIV	D24, D31, D24

0x4246c0 FSQRT	D23, D20

0x4246c4 FMAXNM	D10, D23, D4

0x4246c8 FDIV	D11, D11, D10

0x4246cc FMINNM	D27, D11, D3

0x4246d0 FCMPE	D24, D7

0x4246d4 B.GE	424744

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/calc_dt.cpp: 52 - 75

--------------------------------------------------------------------------------

52:       double dsx = celldx[i];

53:       double dsy = celldy[j];

54:       double cc = soundspeed(i, j) * soundspeed(i, j);

55:       cc = cc + 2.0 * viscosity_a(i, j) / density0(i, j);

56:       cc = std::fmax(std::sqrt(cc), g_small);

57:       double dtct = dtc_safe * std::fmin(dsx, dsy) / cc;

58:       double div = 0.0;

59:       double dv1 = (xvel0(i, j) + xvel0(i + 0, j + 1)) * xarea(i, j);

60:       double dv2 = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) * xarea(i + 1, j + 0);

61:       div = div + dv2 - dv1;

62:       double dtut = dtu_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

63:       dv1 = (yvel0(i, j) + yvel0(i + 1, j + 0)) * yarea(i, j);

64:       dv2 = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) * yarea(i + 0, j + 1);

65:       div = div + dv2 - dv1;

66:       double dtvt = dtv_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

67:       div = div / (2.0 * volume(i, j));

68:       double dtdivt;

69:       if (div < -g_small) {

[...]

75:       dt_min_val0 = std::fmin(mins, dt_min_val0);

Path /

Metric	Value
CQA speedup if no scalar integer	2.19
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.00
Bottlenecks	P10,
Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source	calc_dt.cpp:52-69,calc_dt.cpp:75-75
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.17
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	13.17
CQA cycles if fully vectorized	3.29
Front-end cycles	13.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	5.00
P2 cycles	5.00
P3 cycles	11.00
P4 cycles	5.00
P5 cycles	9.75
P6 cycles	9.75
P7 cycles	9.75
P8 cycles	9.75
P9 cycles	13.17
P10 cycles	12.83
P11 cycles	13.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	6.00 - 3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	105.00
Nb uops	105.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.90
Nb FLOP add-sub	8.00
Nb FLOP mul	9.00
Nb FLOP fma	1.00
Nb FLOP div	5.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.70
Bytes prefetched	0.00
Bytes loaded	304.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	2.19
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.00
Bottlenecks	P10,
Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source	calc_dt.cpp:52-69,calc_dt.cpp:75-75
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.17
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	13.17
CQA cycles if fully vectorized	3.29
Front-end cycles	13.13
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	5.00
P2 cycles	5.00
P3 cycles	11.00
P4 cycles	5.00
P5 cycles	9.75
P6 cycles	9.75
P7 cycles	9.75
P8 cycles	9.75
P9 cycles	13.17
P10 cycles	12.83
P11 cycles	13.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	6.00 - 3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	105.00
Nb uops	105.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	1.90
Nb FLOP add-sub	8.00
Nb FLOP mul	9.00
Nb FLOP fma	1.00
Nb FLOP div	5.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.70
Bytes prefetched	0.00
Bytes loaded	304.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source file and lines	calc_dt.cpp:52-75
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/calc_dt.cpp:52-69,75.

The related source loop is multi-versionned.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.17 to 6.00 cycles (2.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 13.17 to 3.29 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

9: addition or subtraction (1 inside FMA instructions)
10: multiply (1 inside FMA instructions)
5: divide
1: square root

The binary loop is loading 304 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	105
loop length	420
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	5.00	5.00	11.00	5.00	9.75	9.75	9.75	9.75	13.17	12.83	13.00	0.50	0.50
cycles	0.50	0.50	5.00	5.00	11.00	5.00	9.75	9.75	9.75	9.75	13.17	12.83	13.00	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

6.00-3.00

Cycles summary

Front-end	13.13
Overall L1	13.17

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.17 cycles. At this rate:

24% of peak load performance is reached (23.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.61 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 424534

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X28, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W6, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X3, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W2, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X7, X6, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X1, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X6, X0, X28, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X11, X0, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X13, X0, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X10, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X5, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X24, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X10, X0, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X13, X16, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X6, X0, X5, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X8, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X9, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X10, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X8, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X5, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X30, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X27, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X9, X0, X5, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X5, X15, X5, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X0, X2, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR D17, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
MADD X2, X15, X2, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X16, X10, X0, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X10, X15, X10, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X28, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X28, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMINNM D22, D1, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D20, [X2, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D2, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D0, [X5, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D1, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D24, [X10, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D21, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D27, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D26, D20, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D19, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D23, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D25, [X6, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D29, D26, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FADD D31, D27, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D30, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D28, D21, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDR D11, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D21, [X16, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D1, D31, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDR D2, [X13, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D26, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D23, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D0, D30, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D24, [X11, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D10, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D28, [X12, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D30, D2, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D27, [X28, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMINNM D25, D17, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D11, D25, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FSUB D19, D23, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D31, D0, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDR D20, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D27, D24, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D23, D6, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
ORR X3, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMUL D29, D5, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FABS D21, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMAXNM D10, D21, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMAXNM D1, D10, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDIV D28, D30, D28	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1-0.50
FSUB D2, D19, S31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FABS D0, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMAXNM D26, D0, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMAXNM D30, D26, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDIV D19, D23, D1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1-0.50
FMUL D31, D2, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FDIV D25, D29, D30	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1-0.50
FMINNM D21, D19, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMINNM D22, D22, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMADD D20, D20, D20, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FDIV D24, D31, D24	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1-0.50
FSQRT D23, D20	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-16	1-0.50
FMAXNM D10, D23, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDIV D11, D11, D10	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1-0.50
FMINNM D27, D11, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMPE D24, D7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GE 424744 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source file and lines	calc_dt.cpp:52-75
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/calc_dt.cpp:52-69,75.

The related source loop is multi-versionned.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.17 to 6.00 cycles (2.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

9: addition or subtraction (1 inside FMA instructions)
10: multiply (1 inside FMA instructions)
5: divide
1: square root

The binary loop is loading 304 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	105
loop length	420
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	5.00	5.00	11.00	5.00	9.75	9.75	9.75	9.75	13.17	12.83	13.00	0.50	0.50
cycles	0.50	0.50	5.00	5.00	11.00	5.00	9.75	9.75	9.75	9.75	13.17	12.83	13.00	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

6.00-3.00

Cycles summary

Front-end	13.13
Overall L1	13.17

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.17 cycles. At this rate:

24% of peak load performance is reached (23.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.61 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 424534

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X28, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W6, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X3, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W2, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X7, X6, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X1, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X6, X0, X28, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X11, X0, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X13, X0, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X10, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X5, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X24, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X10, X0, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X13, X16, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X6, X0, X5, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X8, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X9, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X10, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [X25, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X8, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X5, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X30, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X27, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X9, X0, X5, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X5, X15, X5, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X0, X2, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR D17, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
MADD X2, X15, X2, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X16, X10, X0, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X10, X15, X10, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X28, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X28, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMINNM D22, D1, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D20, [X2, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D2, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D0, [X5, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D1, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D24, [X10, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D21, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D27, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D26, D20, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D19, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D23, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D25, [X6, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D29, D26, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FADD D31, D27, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D30, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D28, D21, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDR D11, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D21, [X16, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D1, D31, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDR D2, [X13, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D26, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D23, D28, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FADD D0, D30, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D24, [X11, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FABS D10, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D28, [X12, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D30, D2, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D27, [X28, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMINNM D25, D17, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D11, D25, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FSUB D19, D23, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMUL D31, D0, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDR D20, [X14, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D27, D24, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMUL D23, D6, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
ORR X3, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMUL D29, D5, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FABS D21, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMAXNM D10, D21, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMAXNM D1, D10, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDIV D28, D30, D28	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1-0.50
FSUB D2, D19, S31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FABS D0, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMAXNM D26, D0, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMAXNM D30, D26, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDIV D19, D23, D1	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1-0.50
FMUL D31, D2, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FDIV D25, D29, D30	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1-0.50
FMINNM D21, D19, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMINNM D22, D22, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMADD D20, D20, D20, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FDIV D24, D31, D24	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1-0.50
FSQRT D23, D20	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-16	1-0.50
FMAXNM D10, D23, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDIV D11, D11, D10	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1-0.50
FMINNM D27, D11, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMPE D24, D7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GE 424744 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code