OV - exec - Loop 295

0x424520 CMP	W8, W12

0x424524 CSEL	W5, W8, W12, #9

0x424528 ADD	W17, W7, W5

0x42452c CMP	W7, W17

0x424530 B.CS	424758

0x424758 LDR	W14, [SP, #132]    [1]

0x42475c ADD	X0, X0, #1

0x424760 ADD	X15, X15, #1

0x424764 LDR	W17, [SP, #152]    [1]

0x424768 ADD	W4, W14, W0

0x42476c CMP	W17, W4

0x424770 B.LE	424788

0x424774 LDR	W11, [SP, #156]    [1]

0x424778 ORR	W12, WZR, W20

0x42477c LDR	W2, [SP, #128]    [1]

0x424780 SUB	W8, W11, W7

0x424784 B	424520

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/calc_dt.cpp: 51 - 69

--------------------------------------------------------------------------------

51:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

[...]

63:       dv1 = (yvel0(i, j) + yvel0(i + 1, j + 0)) * yarea(i, j);

[...]

69:       if (div < -g_small) {

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	P2, P3, P4, P5,
Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source	calc_dt.cpp:51-51,calc_dt.cpp:63-63,calc_dt.cpp:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	0.38
Front-end cycles	2.13
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.33
P10 cycles	1.33
P11 cycles	1.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	17.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.40
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	15.63
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	P2, P3, P4, P5,
Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source	calc_dt.cpp:51-51,calc_dt.cpp:63-63,calc_dt.cpp:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	0.38
Front-end cycles	2.13
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	2.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.33
P10 cycles	1.33
P11 cycles	1.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	17.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.40
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	15.63
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source file and lines	calc_dt.cpp:51-69
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/calc_dt.cpp:51,63,69.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 15% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.37 cycles (6.67x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.13
Overall L1	2.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

6% of peak load performance is reached (6.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 424758

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
CMP W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
CSEL W5, W8, W12, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W17, W7, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W7, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.CS 424758 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x358>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W14, [SP, #132]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR W17, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD W4, W14, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W17, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 424788 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W11, [SP, #156]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR W12, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR W2, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB W8, W11, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 424520 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp_fn.0]
Source file and lines	calc_dt.cpp:51-69
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/calc_dt.cpp:51,63,69.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 15% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.37 cycles (6.67x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.13
Overall L1	2.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

6% of peak load performance is reached (6.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 424758

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
CMP W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
CSEL W5, W8, W12, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W17, W7, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W7, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.CS 424758 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x358>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W14, [SP, #132]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR W17, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD W4, W14, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W17, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 424788 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W11, [SP, #156]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR W12, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR W2, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB W8, W11, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 424520 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code