OV - exec - Loop 258

	Loop Id: 258	Module: exec	Source: context.h:69-69 [...]	Coverage: 9.25%

0x421e88 LD1D	{Z28.D}, P2/Z, [X16, X0,LSL #3]    [7]

0x421e8c LD1D	{Z5.D}, P1/Z, [X7, X0,LSL #3]    [13]

0x421e90 SUNPKLO	Z9.D, Z16

0x421e94 SUNPKHI	Z8.D, Z16

0x421e98 FCMGE	P4.D, P0/Z, Z28.D, #0

0x421e9c FCMGE	P5.D, P0/Z, Z5.D, #0

0x421ea0 SEL	Z1.D, P4, Z7.D, Z20.D

0x421ea4 UZP1	P3.S, P4.S, P5.S

0x421ea8 MOVPRFX	Z3, Z9

0x421eac MLA	Z3.D, P0/M, Z6.D, Z1.D

0x421eb0 EOR	P6.B, P0/Z, P3.B, P0.B

0x421eb4 MAD	Z1.D, P0/M, Z18.D, Z9.D

0x421eb8 SEL	Z0.S, P6, Z17.S, Z25.S

0x421ebc LD1D	{Z30.D}, P2/Z, [X6, Z1.D,LSL #3]    [6]

0x421ec0 ADD	Z0.S, P6/M, Z0.S, Z27.S

0x421ec4 SUNPKHI	Z2.D, Z0

0x421ec8 MAD	Z2.D, P0/M, Z6.D, Z8.D

0x421ecc LD1D	{Z3.D}, P2/Z, [X23, Z3.D,LSL #3]    [15]

0x421ed0 FCMLT	P7.D, P0/Z, Z28.D, #0

0x421ed4 SUNPKLO	Z29.D, Z0

0x421ed8 MOVPRFX	Z4, Z28

0x421edc FABS	Z4.D, P0/M, Z28.D

0x421ee0 LD1D	{Z0.D}, P1/Z, [X23, Z2.D,LSL #3]    [12]

0x421ee4 FDIV	Z4.D, P0/M, Z4.D, Z30.D

0x421ee8 MAD	Z29.D, P0/M, Z6.D, Z9.D

0x421eec SEL	Z1.D, P7, Z7.D, Z20.D

0x421ef0 LD1D	{Z29.D}, P2/Z, [X23, Z29.D,LSL #3]    [11]

0x421ef4 MAD	Z1.D, P0/M, Z6.D, Z9.D

0x421ef8 FSUB	Z10.D, Z3.D, Z29.D

0x421efc LD1D	{Z2.D}, P2/Z, [X23, Z1.D,LSL #3]    [9]

0x421f00 FABD	Z29.D, P0/M, Z29.D, Z3.D

0x421f04 FSUB	Z30.D, Z2.D, Z3.D

0x421f08 SEL	Z31.S, P3, Z17.S, Z23.S

0x421f0c FMUL	Z10.D, Z10.D, Z30.D

0x421f10 ADD	Z31.S, P3/M, Z31.S, Z26.S

0x421f14 SUNPKLO	Z9.D, Z31

0x421f18 FCMGT	P3.D, P2/Z, Z10.D, #0

0x421f1c FABD	Z2.D, P0/M, Z2.D, Z3.D

0x421f20 FCMGT	P4.D, P0/Z, Z30.D, #0

0x421f24 MOVPRFX	Z1, Z4

0x421f28 FADD	Z1.D, P0/M, Z1.D, #1

0x421f2c LD1D	{Z30.D}, P3/Z, [X4, Z9.D,LSL #3]    [4]

0x421f30 FCMGT	P6.D, P4/Z, Z10.D, #0

0x421f34 MOVPRFX	Z9, Z29

0x421f38 FMINNM	Z9.D, P0/M, Z9.D, Z2.D

0x421f3c FMUL	Z1.D, Z1.D, Z29.D

0x421f40 MOVPRFX	Z10, Z22

0x421f44 FCPY	Z10.D, P6/M, #1.0000000

0x421f48 FSUB	Z29.D, Z21.D, Z4.D

0x421f4c FDIV	Z1.D, P0/M, Z1.D, Z30.D

0x421f50 FMUL	Z2.D, Z29.D, Z2.D

0x421f54 LD1RD	{Z30.D}, P0/Z, [X9]    [3]

0x421f58 FSUBR	Z4.D, P0/M, Z4.D, #1

0x421f5c FDIV	Z2.D, P0/M, Z2.D, Z30.D

0x421f60 FMUL	Z29.D, Z30.D, Z24.D

0x421f64 FMUL	Z4.D, Z4.D, Z10.D

0x421f68 FADD	Z1.D, Z1.D, Z2.D

0x421f6c SEL	Z10.D, P5, Z7.D, Z19.D

0x421f70 FMUL	Z1.D, Z1.D, Z29.D

0x421f74 FMINNM	Z1.D, P0/M, Z1.D, Z9.D

0x421f78 MOVPRFX	Z9, Z8

0x421f7c MLA	Z9.D, P0/M, Z6.D, Z10.D

0x421f80 FMLA	Z3.D, P3/M, Z4.D, Z1.D

0x421f84 LD1D	{Z2.D}, P1/Z, [X23, Z9.D,LSL #3]    [5]

0x421f88 FMUL	Z3.D, Z28.D, Z3.D

0x421f8c FSUB	Z1.D, Z2.D, Z0.D

0x421f90 MAD	Z10.D, P0/M, Z18.D, Z8.D

0x421f94 FCMLT	P8.D, P0/Z, Z5.D, #0

0x421f98 LD1D	{Z10.D}, P1/Z, [X6, Z10.D,LSL #3]    [2]

0x421f9c SEL	Z28.D, P8, Z7.D, Z19.D

0x421fa0 MAD	Z28.D, P0/M, Z6.D, Z8.D

0x421fa4 LD1D	{Z28.D}, P1/Z, [X23, Z28.D,LSL #3]    [8]

0x421fa8 FSUB	Z8.D, Z28.D, Z2.D

0x421fac FMUL	Z9.D, Z1.D, Z8.D

0x421fb0 FABD	Z0.D, P0/M, Z0.D, Z2.D

0x421fb4 FCMGT	P7.D, P1/Z, Z9.D, #0

0x421fb8 FABD	Z28.D, P0/M, Z28.D, Z2.D

0x421fbc MOVPRFX	Z4, Z5

0x421fc0 FABS	Z4.D, P0/M, Z5.D

0x421fc4 FCMGT	P5.D, P0/Z, Z8.D, #0

0x421fc8 FDIV	Z4.D, P0/M, Z4.D, Z10.D

0x421fcc SUNPKHI	Z31.D, Z31

0x421fd0 MOVPRFX	Z10, Z0

0x421fd4 FMINNM	Z10.D, P0/M, Z10.D, Z28.D

0x421fd8 LD1D	{Z31.D}, P7/Z, [X4, Z31.D,LSL #3]    [10]

0x421fdc MOVPRFX	Z1, Z4

0x421fe0 FADD	Z1.D, P0/M, Z1.D, #1

0x421fe4 FSUB	Z8.D, Z21.D, Z4.D

0x421fe8 FCMGT	P4.D, P5/Z, Z9.D, #0

0x421fec FMUL	Z0.D, Z1.D, Z0.D

0x421ff0 FMUL	Z28.D, Z8.D, Z28.D

0x421ff4 FDIV	Z0.D, P0/M, Z0.D, Z31.D

0x421ff8 FDIV	Z28.D, P0/M, Z28.D, Z30.D

0x421ffc FSUBR	Z4.D, P0/M, Z4.D, #1

0x422000 FADD	Z30.D, Z0.D, Z28.D

0x422004 MOVPRFX	Z9, Z22

0x422008 FCPY	Z9.D, P4/M, #1.0000000

0x42200c FMUL	Z29.D, Z30.D, Z29.D

0x422010 FMUL	Z4.D, Z4.D, Z9.D

0x422014 FMINNM	Z29.D, P0/M, Z29.D, Z10.D

0x422018 FMLA	Z2.D, P7/M, Z29.D, Z4.D

0x42201c FMUL	Z5.D, Z5.D, Z2.D

0x422020 ST1D	{Z3.D}, P2, [X24, X0,LSL #3]    [1]

0x422024 ST1D	{Z5.D}, P1, [X5, X0,LSL #3]    [14]

0x422028 ADD	X0, X0, X10

0x42202c WHILELO	P1.D, X0, X8

0x422030 INCW	Z16.S, ALL

0x422034 WHILELO	P2.D, X0, X26

0x422038 B.NE	421e88

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 186 - 211

--------------------------------------------------------------------------------

186:           if (node_flux(i, j) < 0.0) {

[...]

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.23
Bottlenecks	P6, P7,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source	context.h:69-69,advec_mom.cpp:186-186,advec_mom.cpp:197-211
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	44.00
CQA cycles if no scalar integer	44.00
CQA cycles if FP arith vectorized	44.00
CQA cycles if fully vectorized	43.03
Front-end cycles	13.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	4.00
P4 cycles	0.25
P5 cycles	44.00
P6 cycles	44.00
P7 cycles	13.50
P8 cycles	13.50
P9 cycles	7.50
P10 cycles	7.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	6.00 - 3.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	109.00
Nb uops	109.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	3.18
Nb FLOP add-sub	48.00
Nb FLOP mul	52.00
Nb FLOP fma	8.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.36
Bytes prefetched	0.00
Bytes loaded	392.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	80.95
Vectorization ratio load	92.31
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	58.70
Vector-efficiency ratio all	95.77
Vector-efficiency ratio load	94.23
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	91.98

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.23
Bottlenecks	P6, P7,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source	context.h:69-69,advec_mom.cpp:186-186,advec_mom.cpp:197-211
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	44.00
CQA cycles if no scalar integer	44.00
CQA cycles if FP arith vectorized	44.00
CQA cycles if fully vectorized	43.03
Front-end cycles	13.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	4.00
P4 cycles	0.25
P5 cycles	44.00
P6 cycles	44.00
P7 cycles	13.50
P8 cycles	13.50
P9 cycles	7.50
P10 cycles	7.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	6.00 - 3.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	109.00
Nb uops	109.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	3.18
Nb FLOP add-sub	48.00
Nb FLOP mul	52.00
Nb FLOP fma	8.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.36
Bytes prefetched	0.00
Bytes loaded	392.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	80.95
Vectorization ratio load	92.31
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	58.70
Vector-efficiency ratio all	95.77
Vector-efficiency ratio load	94.23
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	91.98

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source file and lines	context.h:69-69
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:186,197-211

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 95% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 44.00 to 43.03 cycles (1.02x speedup).

Details

80% of VPU instructions are used in vector version (process two or more data elements in vector registers):

92% of VPU loads are used in vector version.
58% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 140 FP arithmetical operations:

56: addition or subtraction (8 inside FMA instructions)
60: multiply (8 inside FMA instructions)
24: divide

The binary loop is loading 392 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	109
loop length	436
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	4.00	0.25	44.00	44.00	1.00	1.00	7.50	7.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	4.00	0.25	44.00	44.00	13.50	13.50	7.50	7.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.00-3.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	13.63
Data deps.	2.00
Overall L1	44.00

Vectorization ratios

INT

all	64%
load	92%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
other	29%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	90%

INT+FP

all	80%
load	92%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	58%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 44.00 cycles. At this rate:

9% of peak load performance is reached (8.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.45 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421e88

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z28.D}, P2/Z, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P1/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUNPKLO Z9.D, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z8.D, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGE P4.D, P0/Z, Z28.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FCMGE P5.D, P0/Z, Z5.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SEL Z1.D, P4, Z7.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
UZP1 P3.S, P4.S, P5.S	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
MOVPRFX Z3, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z3.D, P0/M, Z6.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
EOR P6.B, P0/Z, P3.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
MAD Z1.D, P0/M, Z18.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SEL Z0.S, P6, Z17.S, Z25.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z30.D}, P2/Z, [X6, Z1.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD Z0.S, P6/M, Z0.S, Z27.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z2.D, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MAD Z2.D, P0/M, Z6.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z3.D}, P2/Z, [X23, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FCMLT P7.D, P0/Z, Z28.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SUNPKLO Z29.D, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z4, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z4.D, P0/M, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z0.D}, P1/Z, [X23, Z2.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z4.D, P0/M, Z4.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MAD Z29.D, P0/M, Z6.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SEL Z1.D, P7, Z7.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z29.D}, P2/Z, [X23, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z1.D, P0/M, Z6.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FSUB Z10.D, Z3.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z2.D}, P2/Z, [X23, Z1.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FABD Z29.D, P0/M, Z29.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z30.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z31.S, P3, Z17.S, Z23.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, Z10.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD Z31.S, P3/M, Z31.S, Z26.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z9.D, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P3.D, P2/Z, Z10.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FABD Z2.D, P0/M, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P4.D, P0/Z, Z30.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z1, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z1.D, P0/M, Z1.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z30.D}, P3/Z, [X4, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FCMGT P6.D, P4/Z, Z10.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z9, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z9.D, P0/M, Z9.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z1.D, Z1.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z10, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCPY Z10.D, P6/M, #1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z29.D, Z21.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z1.D, P0/M, Z1.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z2.D, Z29.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1RD {Z30.D}, P0/Z, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUBR Z4.D, P0/M, Z4.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z2.D, P0/M, Z2.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z29.D, Z30.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z4.D, Z4.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z1.D, Z1.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z10.D, P5, Z7.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z1.D, Z1.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMINNM Z1.D, P0/M, Z1.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z9, Z8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z9.D, P0/M, Z6.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMLA Z3.D, P3/M, Z4.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z2.D}, P1/Z, [X23, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z3.D, Z28.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z1.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MAD Z10.D, P0/M, Z18.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FCMLT P8.D, P0/Z, Z5.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
LD1D {Z10.D}, P1/Z, [X6, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SEL Z28.D, P8, Z7.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MAD Z28.D, P0/M, Z6.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z28.D}, P1/Z, [X23, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z8.D, Z28.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z9.D, Z1.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FABD Z0.D, P0/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P7.D, P1/Z, Z9.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FABD Z28.D, P0/M, Z28.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z4, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z4.D, P0/M, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P5.D, P0/Z, Z8.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FDIV Z4.D, P0/M, Z4.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
SUNPKHI Z31.D, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z10, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z10.D, P0/M, Z10.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z31.D}, P7/Z, [X4, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z1, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z1.D, P0/M, Z1.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z8.D, Z21.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P4.D, P5/Z, Z9.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z0.D, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z28.D, Z8.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z0.D, P0/M, Z0.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIV Z28.D, P0/M, Z28.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FSUBR Z4.D, P0/M, Z4.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z30.D, Z0.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z9, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCPY Z9.D, P4/M, #1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z29.D, Z30.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z4.D, Z4.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMINNM Z29.D, P0/M, Z29.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z2.D, P7/M, Z29.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z5.D, Z5.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z3.D}, P2, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ST1D {Z5.D}, P1, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X0, X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P1.D, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
INCW Z16.S, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
WHILELO P2.D, X0, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 421e88 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source file and lines	context.h:69-69
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:186,197-211

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

80% of VPU instructions are used in vector version (process two or more data elements in vector registers):

92% of VPU loads are used in vector version.
58% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 140 FP arithmetical operations:

56: addition or subtraction (8 inside FMA instructions)
60: multiply (8 inside FMA instructions)
24: divide

The binary loop is loading 392 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	109
loop length	436
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	4.00	0.25	44.00	44.00	1.00	1.00	7.50	7.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	4.00	0.25	44.00	44.00	13.50	13.50	7.50	7.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.00-3.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	13.63
Data deps.	2.00
Overall L1	44.00

Vectorization ratios

INT

all	64%
load	92%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
other	29%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	90%

INT+FP

all	80%
load	92%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	58%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 44.00 cycles. At this rate:

9% of peak load performance is reached (8.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.45 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421e88

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z28.D}, P2/Z, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P1/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SUNPKLO Z9.D, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z8.D, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGE P4.D, P0/Z, Z28.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FCMGE P5.D, P0/Z, Z5.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SEL Z1.D, P4, Z7.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
UZP1 P3.S, P4.S, P5.S	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
MOVPRFX Z3, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z3.D, P0/M, Z6.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
EOR P6.B, P0/Z, P3.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
MAD Z1.D, P0/M, Z18.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SEL Z0.S, P6, Z17.S, Z25.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z30.D}, P2/Z, [X6, Z1.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD Z0.S, P6/M, Z0.S, Z27.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z2.D, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MAD Z2.D, P0/M, Z6.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z3.D}, P2/Z, [X23, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FCMLT P7.D, P0/Z, Z28.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SUNPKLO Z29.D, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z4, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z4.D, P0/M, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z0.D}, P1/Z, [X23, Z2.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z4.D, P0/M, Z4.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
MAD Z29.D, P0/M, Z6.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
SEL Z1.D, P7, Z7.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z29.D}, P2/Z, [X23, Z29.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MAD Z1.D, P0/M, Z6.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FSUB Z10.D, Z3.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z2.D}, P2/Z, [X23, Z1.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FABD Z29.D, P0/M, Z29.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z30.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z31.S, P3, Z17.S, Z23.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z10.D, Z10.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADD Z31.S, P3/M, Z31.S, Z26.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z9.D, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P3.D, P2/Z, Z10.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FABD Z2.D, P0/M, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P4.D, P0/Z, Z30.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z1, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z1.D, P0/M, Z1.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z30.D}, P3/Z, [X4, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FCMGT P6.D, P4/Z, Z10.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z9, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z9.D, P0/M, Z9.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z1.D, Z1.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z10, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCPY Z10.D, P6/M, #1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z29.D, Z21.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z1.D, P0/M, Z1.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z2.D, Z29.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1RD {Z30.D}, P0/Z, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUBR Z4.D, P0/M, Z4.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIV Z2.D, P0/M, Z2.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z29.D, Z30.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z4.D, Z4.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z1.D, Z1.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z10.D, P5, Z7.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z1.D, Z1.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMINNM Z1.D, P0/M, Z1.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z9, Z8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MLA Z9.D, P0/M, Z6.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FMLA Z3.D, P3/M, Z4.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z2.D}, P1/Z, [X23, Z9.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z3.D, Z28.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FSUB Z1.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MAD Z10.D, P0/M, Z18.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
FCMLT P8.D, P0/Z, Z5.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
LD1D {Z10.D}, P1/Z, [X6, Z10.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
SEL Z28.D, P8, Z7.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MAD Z28.D, P0/M, Z6.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2
LD1D {Z28.D}, P1/Z, [X23, Z28.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z8.D, Z28.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z9.D, Z1.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FABD Z0.D, P0/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P7.D, P1/Z, Z9.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FABD Z28.D, P0/M, Z28.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z4, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z4.D, P0/M, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P5.D, P0/Z, Z8.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FDIV Z4.D, P0/M, Z4.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
SUNPKHI Z31.D, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z10, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z10.D, P0/M, Z10.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z31.D}, P7/Z, [X4, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z1, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z1.D, P0/M, Z1.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z8.D, Z21.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P4.D, P5/Z, Z9.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z0.D, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z28.D, Z8.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z0.D, P0/M, Z0.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIV Z28.D, P0/M, Z28.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FSUBR Z4.D, P0/M, Z4.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z30.D, Z0.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z9, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCPY Z9.D, P4/M, #1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z29.D, Z30.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z4.D, Z4.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMINNM Z29.D, P0/M, Z29.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z2.D, P7/M, Z29.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z5.D, Z5.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z3.D}, P2, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ST1D {Z5.D}, P1, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X0, X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P1.D, X0, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
INCW Z16.S, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
WHILELO P2.D, X0, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 421e88 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code