OV - exec - Loop 254

	Loop Id: 254	Module: exec	Source: context.h:69-69 [...]	Coverage: 8.88%

0x421b00 LD1D	{Z23.D}, P2/Z, [X6, X0,LSL #3]    [12]

0x421b04 LD1D	{Z4.D}, P1/Z, [X8, X0,LSL #3]    [1]

0x421b08 FCMGE	P3.D, P0/Z, Z23.D, #0

0x421b0c FCMGE	P5.D, P0/Z, Z4.D, #0

0x421b10 MOVPRFX	Z20, Z5

0x421b14 SUB	Z20.S, Z20.S, #1

0x421b18 UZP1	P6.S, P3.S, P5.S

0x421b1c EOR	P4.B, P0/Z, P6.B, P0.B

0x421b20 MOVPRFX	Z20.S, P4/M, Z5.S

0x421b24 ADD	Z20.S, P4/M, Z20.S, Z18.S

0x421b28 MOVPRFX	Z24, Z5

0x421b2c ADD	Z24.S, Z24.S, #1

0x421b30 SUNPKLO	Z2.D, Z5

0x421b34 SUNPKLO	Z3.D, Z24

0x421b38 SUNPKLO	Z19.D, Z20

0x421b3c SEL	Z22.D, P3, Z2.D, Z3.D

0x421b40 LD1D	{Z27.D}, P2/Z, [X7, Z19.D,LSL #3]    [14]

0x421b44 LD1D	{Z21.D}, P2/Z, [X7, Z22.D,LSL #3]    [5]

0x421b48 LD1D	{Z26.D}, P2/Z, [X16, Z22.D,LSL #3]    [3]

0x421b4c FSUB	Z29.D, Z21.D, Z27.D

0x421b50 SUNPKHI	Z0.D, Z20

0x421b54 FCMLT	P7.D, P0/Z, Z23.D, #0

0x421b58 SEL	Z25.D, P7, Z2.D, Z3.D

0x421b5c LD1D	{Z30.D}, P2/Z, [X7, Z25.D,LSL #3]    [9]

0x421b60 FSUB	Z20.D, Z30.D, Z21.D

0x421b64 LD1D	{Z28.D}, P1/Z, [X7, Z0.D,LSL #3]    [2]

0x421b68 FMUL	Z3.D, Z20.D, Z29.D

0x421b6c SEL	Z19.S, P6, Z5.S, Z24.S

0x421b70 FCMGT	P3.D, P2/Z, Z3.D, #0

0x421b74 ADD	Z19.S, P6/M, Z19.S, Z17.S

0x421b78 SUNPKHI	Z1.D, Z5

0x421b7c FABD	Z27.D, P0/M, Z27.D, Z21.D

0x421b80 FABD	Z30.D, P0/M, Z30.D, Z21.D

0x421b84 SUNPKLO	Z0.D, Z19

0x421b88 MOVPRFX	Z31, Z23

0x421b8c FABS	Z31.D, P0/M, Z23.D

0x421b90 LD1D	{Z2.D}, P3/Z, [X5, Z0.D,LSL #3]    [10]

0x421b94 FDIV	Z31.D, P0/M, Z31.D, Z26.D

0x421b98 FCMGT	P4.D, P0/Z, Z20.D, #0

0x421b9c MOVPRFX	Z26, Z27

0x421ba0 FMINNM	Z26.D, P0/M, Z26.D, Z30.D

0x421ba4 LD1D	{Z20.D}, P2/Z, [X30, X0,LSL #3]    [11]

0x421ba8 MOVPRFX	Z25, Z31

0x421bac FADD	Z25.D, P0/M, Z25.D, #1

0x421bb0 FSUB	Z29.D, Z7.D, Z31.D

0x421bb4 FMUL	Z27.D, Z25.D, Z27.D

0x421bb8 FMUL	Z30.D, Z29.D, Z30.D

0x421bbc FDIV	Z27.D, P0/M, Z27.D, Z2.D

0x421bc0 FDIV	Z30.D, P0/M, Z30.D, Z20.D

0x421bc4 SUNPKHI	Z24.D, Z24

0x421bc8 FADD	Z0.D, Z27.D, Z30.D

0x421bcc SEL	Z25.D, P5, Z1.D, Z24.D

0x421bd0 SUNPKHI	Z22.D, Z19

0x421bd4 LD1D	{Z30.D}, P1/Z, [X7, Z25.D,LSL #3]    [8]

0x421bd8 FMUL	Z19.D, Z20.D, Z6.D

0x421bdc FCMLT	P8.D, P0/Z, Z4.D, #0

0x421be0 LD1D	{Z20.D}, P1/Z, [X16, Z25.D,LSL #3]    [6]

0x421be4 FMUL	Z27.D, Z0.D, Z19.D

0x421be8 FCMGT	P6.D, P4/Z, Z3.D, #0

0x421bec FMINNM	Z27.D, P0/M, Z27.D, Z26.D

0x421bf0 MOVPRFX	Z3, Z16

0x421bf4 FCPY	Z3.D, P6/M, #1.0000000

0x421bf8 FSUBR	Z31.D, P0/M, Z31.D, #1

0x421bfc FMUL	Z31.D, Z31.D, Z3.D

0x421c00 MOVPRFX	Z2, Z21

0x421c04 FMLA	Z2.D, P3/M, Z31.D, Z27.D

0x421c08 SEL	Z21.D, P8, Z1.D, Z24.D

0x421c0c FMUL	Z29.D, Z23.D, Z2.D

0x421c10 LD1D	{Z1.D}, P1/Z, [X7, Z21.D,LSL #3]    [13]

0x421c14 FSUB	Z23.D, Z30.D, Z28.D

0x421c18 FSUB	Z26.D, Z1.D, Z30.D

0x421c1c FABD	Z1.D, P0/M, Z1.D, Z30.D

0x421c20 LD1D	{Z24.D}, P1/Z, [X24, X0,LSL #3]    [7]

0x421c24 FMUL	Z3.D, Z23.D, Z26.D

0x421c28 FABD	Z28.D, P0/M, Z28.D, Z30.D

0x421c2c FCMGT	P5.D, P1/Z, Z3.D, #0

0x421c30 MOVPRFX	Z31, Z28

0x421c34 FMINNM	Z31.D, P0/M, Z31.D, Z1.D

0x421c38 LD1D	{Z22.D}, P5/Z, [X5, Z22.D,LSL #3]    [4]

0x421c3c MOVPRFX	Z19, Z4

0x421c40 FABS	Z19.D, P0/M, Z4.D

0x421c44 FCMGT	P7.D, P0/Z, Z26.D, #0

0x421c48 FDIV	Z19.D, P0/M, Z19.D, Z20.D

0x421c4c FMUL	Z21.D, Z24.D, Z6.D

0x421c50 MOVPRFX	Z0, Z19

0x421c54 FADD	Z0.D, P0/M, Z0.D, #1

0x421c58 FSUB	Z27.D, Z7.D, Z19.D

0x421c5c FMUL	Z28.D, Z0.D, Z28.D

0x421c60 FMUL	Z25.D, Z27.D, Z1.D

0x421c64 FDIV	Z28.D, P0/M, Z28.D, Z22.D

0x421c68 FDIV	Z25.D, P0/M, Z25.D, Z24.D

0x421c6c FSUBR	Z19.D, P0/M, Z19.D, #1

0x421c70 FADD	Z2.D, Z28.D, Z25.D

0x421c74 FCMGT	P3.D, P7/Z, Z3.D, #0

0x421c78 FMUL	Z20.D, Z2.D, Z21.D

0x421c7c MOVPRFX	Z1, Z16

0x421c80 FCPY	Z1.D, P3/M, #1.0000000

0x421c84 FMINNM	Z20.D, P0/M, Z20.D, Z31.D

0x421c88 FMUL	Z23.D, Z19.D, Z1.D

0x421c8c MOVPRFX	Z26, Z30

0x421c90 FMLA	Z26.D, P5/M, Z23.D, Z20.D

0x421c94 FMUL	Z4.D, Z4.D, Z26.D

0x421c98 ST1D	{Z29.D}, P2, [X3, X0,LSL #3]    [16]

0x421c9c ST1D	{Z4.D}, P1, [X4, X0,LSL #3]    [15]

0x421ca0 ADD	X0, X0, X10

0x421ca4 WHILELO	P1.D, X0, X23

0x421ca8 INCW	Z5.S, ALL

0x421cac WHILELO	P2.D, X0, X2

0x421cb0 B.NE	421b00

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 114 - 139

--------------------------------------------------------------------------------

114:           if (node_flux(i, j) < 0.0) {

[...]

120:             upwind = i - 1;

121:             donor = i;

122:             downwind = i + 1;

123:             dif = upwind;

124:           }

125:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j));

126:           width = celldx[i];

127:           vdiffuw = vel1(donor, j) - vel1(upwind, j);

128:           vdiffdw = vel1(downwind, j) - vel1(donor, j);

129:           limiter = 0.0;

130:           if (vdiffuw * vdiffdw > 0.0) {

131:             auw = std::fabs(vdiffuw);

132:             adw = std::fabs(vdiffdw);

133:             wind = 1.0;

134:             if (vdiffdw <= 0.0) wind = -1.0;

135:             limiter =

136:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw);

137:           }

138:           advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter;

139:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.11
Bottlenecks	P6, P7,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.6]
Source	context.h:69-69,advec_mom.cpp:114-114,advec_mom.cpp:120-139
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	43.50
CQA cycles if no scalar integer	43.50
CQA cycles if FP arith vectorized	43.50
CQA cycles if fully vectorized	42.53
Front-end cycles	13.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	4.00
P4 cycles	0.25
P5 cycles	43.50
P6 cycles	43.50
P7 cycles	14.00
P8 cycles	14.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	6.00 - 3.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	109.00
Nb uops	109.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	3.31
Nb FLOP add-sub	48.00
Nb FLOP mul	56.00
Nb FLOP fma	8.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.77
Bytes prefetched	0.00
Bytes loaded	448.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	78.10
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	54.00
Vector-efficiency ratio all	96.49
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	92.63

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.11
Bottlenecks	P6, P7,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.6]
Source	context.h:69-69,advec_mom.cpp:114-114,advec_mom.cpp:120-139
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	43.50
CQA cycles if no scalar integer	43.50
CQA cycles if FP arith vectorized	43.50
CQA cycles if fully vectorized	42.53
Front-end cycles	13.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	4.00
P4 cycles	0.25
P5 cycles	43.50
P6 cycles	43.50
P7 cycles	14.00
P8 cycles	14.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	6.00 - 3.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	109.00
Nb uops	109.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	3.31
Nb FLOP add-sub	48.00
Nb FLOP mul	56.00
Nb FLOP fma	8.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.77
Bytes prefetched	0.00
Bytes loaded	448.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	78.10
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	54.00
Vector-efficiency ratio all	96.49
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	92.63

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.6]
Source file and lines	context.h:69-69
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:114,120-139

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 96% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 43.50 to 42.53 cycles (1.02x speedup).

Details

78% of VPU instructions are used in vector version (process two or more data elements in vector registers):

54% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 144 FP arithmetical operations:

56: addition or subtraction (8 inside FMA instructions)
64: multiply (8 inside FMA instructions)
24: divide

The binary loop is loading 448 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.28 FP operations per loaded or stored byte.

General properties

nb instructions	109
loop length	436
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	4.00	0.25	43.50	43.50	1.00	1.00	8.00	8.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	4.00	0.25	43.50	43.50	14.00	14.00	8.00	8.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.00-3.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	13.63
Data deps.	2.00
Overall L1	43.50

Vectorization ratios

INT

all	57%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	90%

INT+FP

all	78%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	54%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 43.50 cycles. At this rate:

10% of peak load performance is reached (10.30 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421b00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z23.D}, P2/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z4.D}, P1/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FCMGE P3.D, P0/Z, Z23.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FCMGE P5.D, P0/Z, Z4.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z20, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUB Z20.S, Z20.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
UZP1 P6.S, P3.S, P5.S	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
EOR P4.B, P0/Z, P6.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
MOVPRFX Z20.S, P4/M, Z5.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z20.S, P4/M, Z20.S, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z24, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z24.S, Z24.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z2.D, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z3.D, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z19.D, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z22.D, P3, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z27.D}, P2/Z, [X7, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z21.D}, P2/Z, [X7, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P2/Z, [X16, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z29.D, Z21.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z0.D, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMLT P7.D, P0/Z, Z23.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SEL Z25.D, P7, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z30.D}, P2/Z, [X7, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z20.D, Z30.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z28.D}, P1/Z, [X7, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z3.D, Z20.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
SEL Z19.S, P6, Z5.S, Z24.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P3.D, P2/Z, Z3.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
ADD Z19.S, P6/M, Z19.S, Z17.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z1.D, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z27.D, P0/M, Z27.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z30.D, P0/M, Z30.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z0.D, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z31, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z31.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z2.D}, P3/Z, [X5, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z31.D, P0/M, Z31.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FCMGT P4.D, P0/Z, Z20.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z26, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z26.D, P0/M, Z26.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z20.D}, P2/Z, [X30, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z25, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z25.D, P0/M, Z25.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z29.D, Z7.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z27.D, Z25.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z30.D, Z29.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z27.D, P0/M, Z27.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIV Z30.D, P0/M, Z30.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
SUNPKHI Z24.D, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z0.D, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z25.D, P5, Z1.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z22.D, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z30.D}, P1/Z, [X7, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z19.D, Z20.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FCMLT P8.D, P0/Z, Z4.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
LD1D {Z20.D}, P1/Z, [X16, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z27.D, Z0.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FCMGT P6.D, P4/Z, Z3.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMINNM Z27.D, P0/M, Z27.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z3, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCPY Z3.D, P6/M, #1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUBR Z31.D, P0/M, Z31.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z31.D, Z31.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z2, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z2.D, P3/M, Z31.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
SEL Z21.D, P8, Z1.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z29.D, Z23.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z1.D}, P1/Z, [X7, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z23.D, Z30.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z26.D, Z1.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z1.D, P0/M, Z1.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z24.D}, P1/Z, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z3.D, Z23.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FABD Z28.D, P0/M, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P5.D, P1/Z, Z3.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z31, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z31.D, P0/M, Z31.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z22.D}, P5/Z, [X5, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z19, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z19.D, P0/M, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P7.D, P0/Z, Z26.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FDIV Z19.D, P0/M, Z19.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z21.D, Z24.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z0, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z0.D, P0/M, Z0.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z27.D, Z7.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z28.D, Z0.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z25.D, Z27.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z28.D, P0/M, Z28.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIV Z25.D, P0/M, Z25.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FSUBR Z19.D, P0/M, Z19.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z2.D, Z28.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P3.D, P7/Z, Z3.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z20.D, Z2.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z1, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCPY Z1.D, P3/M, #1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z20.D, P0/M, Z20.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, Z19.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z26, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z26.D, P5/M, Z23.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z4.D, Z4.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z29.D}, P2, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ST1D {Z4.D}, P1, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X0, X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P1.D, X0, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
INCW Z5.S, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
WHILELO P2.D, X0, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 421b00 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.6]
Source file and lines	context.h:69-69
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:114,120-139

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

78% of VPU instructions are used in vector version (process two or more data elements in vector registers):

54% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 144 FP arithmetical operations:

56: addition or subtraction (8 inside FMA instructions)
64: multiply (8 inside FMA instructions)
24: divide

The binary loop is loading 448 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.28 FP operations per loaded or stored byte.

General properties

nb instructions	109
loop length	436
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	4.00	0.25	43.50	43.50	1.00	1.00	8.00	8.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	4.00	0.25	43.50	43.50	14.00	14.00	8.00	8.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	6.00-3.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	13.63
Data deps.	2.00
Overall L1	43.50

Vectorization ratios

INT

all	57%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	90%

INT+FP

all	78%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	54%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 43.50 cycles. At this rate:

10% of peak load performance is reached (10.30 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421b00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z23.D}, P2/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z4.D}, P1/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FCMGE P3.D, P0/Z, Z23.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FCMGE P5.D, P0/Z, Z4.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z20, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUB Z20.S, Z20.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
UZP1 P6.S, P3.S, P5.S	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1
EOR P4.B, P0/Z, P6.B, P0.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1
MOVPRFX Z20.S, P4/M, Z5.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z20.S, P4/M, Z20.S, Z18.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z24, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ADD Z24.S, Z24.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z2.D, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z3.D, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z19.D, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z22.D, P3, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z27.D}, P2/Z, [X7, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z21.D}, P2/Z, [X7, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P2/Z, [X16, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z29.D, Z21.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z0.D, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMLT P7.D, P0/Z, Z23.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
SEL Z25.D, P7, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z30.D}, P2/Z, [X7, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z20.D, Z30.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z28.D}, P1/Z, [X7, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z3.D, Z20.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
SEL Z19.S, P6, Z5.S, Z24.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P3.D, P2/Z, Z3.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
ADD Z19.S, P6/M, Z19.S, Z17.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z1.D, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z27.D, P0/M, Z27.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z30.D, P0/M, Z30.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKLO Z0.D, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z31, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z31.D, P0/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z2.D}, P3/Z, [X5, Z0.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FDIV Z31.D, P0/M, Z31.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FCMGT P4.D, P0/Z, Z20.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z26, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z26.D, P0/M, Z26.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z20.D}, P2/Z, [X30, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z25, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z25.D, P0/M, Z25.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z29.D, Z7.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z27.D, Z25.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z30.D, Z29.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z27.D, P0/M, Z27.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIV Z30.D, P0/M, Z30.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
SUNPKHI Z24.D, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z0.D, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SEL Z25.D, P5, Z1.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
SUNPKHI Z22.D, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z30.D}, P1/Z, [X7, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z19.D, Z20.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FCMLT P8.D, P0/Z, Z4.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
LD1D {Z20.D}, P1/Z, [X16, Z25.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z27.D, Z0.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FCMGT P6.D, P4/Z, Z3.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMINNM Z27.D, P0/M, Z27.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
MOVPRFX Z3, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCPY Z3.D, P6/M, #1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUBR Z31.D, P0/M, Z31.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z31.D, Z31.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z2, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z2.D, P3/M, Z31.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
SEL Z21.D, P8, Z1.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z29.D, Z23.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z1.D}, P1/Z, [X7, Z21.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z23.D, Z30.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z26.D, Z1.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABD Z1.D, P0/M, Z1.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z24.D}, P1/Z, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z3.D, Z23.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FABD Z28.D, P0/M, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P5.D, P1/Z, Z3.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
MOVPRFX Z31, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z31.D, P0/M, Z31.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z22.D}, P5/Z, [X5, Z22.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
MOVPRFX Z19, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FABS Z19.D, P0/M, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P7.D, P0/Z, Z26.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FDIV Z19.D, P0/M, Z19.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMUL Z21.D, Z24.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z0, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z0.D, P0/M, Z0.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z27.D, Z7.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z28.D, Z0.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z25.D, Z27.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z28.D, P0/M, Z28.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIV Z25.D, P0/M, Z25.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FSUBR Z19.D, P0/M, Z19.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z2.D, Z28.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCMGT P3.D, P7/Z, Z3.D, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1
FMUL Z20.D, Z2.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z1, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FCPY Z1.D, P3/M, #1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMINNM Z20.D, P0/M, Z20.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z23.D, Z19.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVPRFX Z26, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMLA Z26.D, P5/M, Z23.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z4.D, Z4.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z29.D}, P2, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ST1D {Z4.D}, P1, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X0, X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P1.D, X0, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
INCW Z5.S, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
WHILELO P2.D, X0, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 421b00 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code