| Loop Id: 229 | Module: exec | Source: advec_mom.cpp:98-100 | Coverage: 1.41% |
|---|
| Loop Id: 229 | Module: exec | Source: advec_mom.cpp:98-100 | Coverage: 1.41% |
|---|
0x420f60 LD1D {Z0.D}, P0/Z, [X6, X0,LSL #3] [10] |
0x420f64 LD1D {Z1.D}, P0/Z, [X5, X0,LSL #3] [1] |
0x420f68 LD1D {Z2.D}, P0/Z, [X7, X0,LSL #3] [5] |
0x420f6c LD1D {Z6.D}, P0/Z, [X2, X0,LSL #3] [4] |
0x420f70 LD1D {Z4.D}, P0/Z, [X11, X0,LSL #3] [12] |
0x420f74 LD1D {Z7.D}, P0/Z, [X9, X0,LSL #3] [9] |
0x420f78 LD1D {Z16.D}, P0/Z, [X12, X0,LSL #3] [8] |
0x420f7c LD1D {Z18.D}, P0/Z, [X10, X0,LSL #3] [7] |
0x420f80 FMUL Z3.D, Z1.D, Z0.D |
0x420f84 FMUL Z17.D, Z7.D, Z4.D |
0x420f88 FMAD Z6.D, P1/M, Z2.D, Z3.D |
0x420f8c FMAD Z18.D, P1/M, Z16.D, Z17.D |
0x420f90 FADD Z19.D, Z6.D, Z18.D |
0x420f94 FMUL Z20.D, Z19.D, Z5.D |
0x420f98 ST1D {Z20.D}, P0, [X28, X0,LSL #3] [3] |
0x420f9c LD1D {Z21.D}, P0/Z, [X8, X0,LSL #3] [11] |
0x420fa0 LD1D {Z22.D}, P0/Z, [X14, X0,LSL #3] [6] |
0x420fa4 FSUB Z23.D, Z22.D, Z21.D |
0x420fa8 FADD Z24.D, Z23.D, Z20.D |
0x420fac ST1D {Z24.D}, P0, [X3, X0,LSL #3] [2] |
0x420fb0 ADD X0, X0, X15 |
0x420fb4 WHILELO P0.D, X0, X1 |
0x420fb8 B.NE 420f60 |
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 98 - 100 |
-------------------------------------------------------------------------------- |
98: node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) + |
99: density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0)); |
100: node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i - 1, j + 0) + node_flux(i, j); |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.50 |
| Bottlenecks | P10, P11, |
| Function | advec_mom_kernel(int, int, int, int, clover::Buffer2D |
| Source | advec_mom.cpp:98-100 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 6.00 |
| CQA cycles if no scalar integer | 6.00 |
| CQA cycles if FP arith vectorized | 6.00 |
| CQA cycles if fully vectorized | 6.00 |
| Front-end cycles | 2.88 |
| DIV/SQRT cycles | 0.50 |
| P0 cycles | 0.50 |
| P1 cycles | 0.50 |
| P2 cycles | 0.25 |
| P3 cycles | 1.00 |
| P4 cycles | 0.25 |
| P5 cycles | 4.00 |
| P6 cycles | 4.00 |
| P7 cycles | 4.00 |
| P8 cycles | 4.00 |
| P9 cycles | 6.00 |
| P10 cycles | 6.00 |
| P11 cycles | 0.00 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 23.00 |
| Nb uops | 23.00 |
| Nb loads | NA |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 6.67 |
| Nb FLOP add-sub | 12.00 |
| Nb FLOP mul | 12.00 |
| Nb FLOP fma | 8.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 64.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 320.00 |
| Bytes stored | 64.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.50 |
| Bottlenecks | P10, P11, |
| Function | advec_mom_kernel(int, int, int, int, clover::Buffer2D |
| Source | advec_mom.cpp:98-100 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 6.00 |
| CQA cycles if no scalar integer | 6.00 |
| CQA cycles if FP arith vectorized | 6.00 |
| CQA cycles if fully vectorized | 6.00 |
| Front-end cycles | 2.88 |
| DIV/SQRT cycles | 0.50 |
| P0 cycles | 0.50 |
| P1 cycles | 0.50 |
| P2 cycles | 0.25 |
| P3 cycles | 1.00 |
| P4 cycles | 0.25 |
| P5 cycles | 4.00 |
| P6 cycles | 4.00 |
| P7 cycles | 4.00 |
| P8 cycles | 4.00 |
| P9 cycles | 6.00 |
| P10 cycles | 6.00 |
| P11 cycles | 0.00 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 23.00 |
| Nb uops | 23.00 |
| Nb loads | NA |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 6.67 |
| Nb FLOP add-sub | 12.00 |
| Nb FLOP mul | 12.00 |
| Nb FLOP fma | 8.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 64.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 320.00 |
| Bytes stored | 64.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| nb instructions | 23 |
| loop length | 92 |
| nb stack references | 0 |
| front end | 2.88 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 0.50 | 0.25 | 1.00 | 0.25 | 4.00 | 4.00 | 1.00 | 1.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 |
| cycles | 0.50 | 0.50 | 0.50 | 0.25 | 1.00 | 0.25 | 4.00 | 4.00 | 4.00 | 4.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 2.88 |
| Data deps. | 1.00 |
| Overall L1 | 6.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LD1D {Z0.D}, P0/Z, [X6, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD1D {Z1.D}, P0/Z, [X5, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD1D {Z2.D}, P0/Z, [X7, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD1D {Z6.D}, P0/Z, [X2, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD1D {Z4.D}, P0/Z, [X11, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD1D {Z7.D}, P0/Z, [X9, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD1D {Z16.D}, P0/Z, [X12, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD1D {Z18.D}, P0/Z, [X10, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| FMUL Z3.D, Z1.D, Z0.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| FMUL Z17.D, Z7.D, Z4.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| FMAD Z6.D, P1/M, Z2.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| FMAD Z18.D, P1/M, Z16.D, Z17.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| FADD Z19.D, Z6.D, Z18.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| FMUL Z20.D, Z19.D, Z5.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| ST1D {Z20.D}, P0, [X28, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| LD1D {Z21.D}, P0/Z, [X8, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD1D {Z22.D}, P0/Z, [X14, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| FSUB Z23.D, Z22.D, Z21.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| FADD Z24.D, Z23.D, Z20.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| ST1D {Z24.D}, P0, [X3, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| ADD X0, X0, X15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| WHILELO P0.D, X0, X1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 |
| B.NE 420f60 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x180> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| nb instructions | 23 |
| loop length | 92 |
| nb stack references | 0 |
| front end | 2.88 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 0.50 | 0.25 | 1.00 | 0.25 | 4.00 | 4.00 | 1.00 | 1.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 |
| cycles | 0.50 | 0.50 | 0.50 | 0.25 | 1.00 | 0.25 | 4.00 | 4.00 | 4.00 | 4.00 | 6.00 | 6.00 | 0.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 2.88 |
| Data deps. | 1.00 |
| Overall L1 | 6.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LD1D {Z0.D}, P0/Z, [X6, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD1D {Z1.D}, P0/Z, [X5, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD1D {Z2.D}, P0/Z, [X7, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD1D {Z6.D}, P0/Z, [X2, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD1D {Z4.D}, P0/Z, [X11, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD1D {Z7.D}, P0/Z, [X9, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD1D {Z16.D}, P0/Z, [X12, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD1D {Z18.D}, P0/Z, [X10, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| FMUL Z3.D, Z1.D, Z0.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| FMUL Z17.D, Z7.D, Z4.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| FMAD Z6.D, P1/M, Z2.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| FMAD Z18.D, P1/M, Z16.D, Z17.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| FADD Z19.D, Z6.D, Z18.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| FMUL Z20.D, Z19.D, Z5.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| ST1D {Z20.D}, P0, [X28, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| LD1D {Z21.D}, P0/Z, [X8, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| LD1D {Z22.D}, P0/Z, [X14, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 0.50 |
| FSUB Z23.D, Z22.D, Z21.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| FADD Z24.D, Z23.D, Z20.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| ST1D {Z24.D}, P0, [X3, X0,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| ADD X0, X0, X15 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| WHILELO P0.D, X0, X1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 |
| B.NE 420f60 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x180> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |