OV - exec - Loop 222

	Loop Id: 222	Module: exec	Source: advec_mom.cpp:64-66 [...]	Coverage: 0.02%

0x420b2c LDR	X24, [X11]

0x420b30 SBFM	X23, X2, #0, #31

0x420b34 ADD	X16, X17, #1

0x420b38 MOVZ	X0, #0

0x420b3c WHILELO	P0.D, XZR, X30

0x420b40 LDR	X6, [X9]

0x420b44 LDR	X18, [X10]

0x420b48 MADD	X2, X17, X24, X23

0x420b4c LDR	X3, [X12]

0x420b50 MADD	X25, X17, X6, X23

0x420b54 LDR	X22, [X11, #16]

0x420b58 MADD	X26, X17, X18, X23

0x420b5c LDR	X7, [X12, #16]

0x420b60 MADD	X17, X17, X3, X3

0x420b64 LDR	X24, [X9, #16]

0x420b68 ADD	X1, X22, X2,LSL #3

0x420b6c LDR	X22, [X10, #16]

0x420b70 SUB	X4, X17, X3

0x420b74 ADD	X5, X17, X23

0x420b78 ADD	X23, X4, X23

0x420b7c ADD	X18, X7, X5,LSL #3

0x420b80 ADD	X6, X7, X23,LSL #3

0x420b84 ADD	X25, X24, X25,LSL #3

0x420b88 ADD	X26, X22, X26,LSL #3

  (221) 0x420b8c LD1D	{Z1.D}, P0/Z, [X1, X0,LSL #3]

  (221) 0x420b90 ST1D	{Z1.D}, P0, [X25, X0,LSL #3]

  (221) 0x420b94 LD1D	{Z0.D}, P0/Z, [X18, X0,LSL #3]

  (221) 0x420b98 LD1D	{Z2.D}, P0/Z, [X6, X0,LSL #3]

  (221) 0x420b9c FADD	Z3.D, Z0.D, Z1.D

  (221) 0x420ba0 FSUB	Z4.D, Z3.D, Z2.D

  (221) 0x420ba4 ST1D	{Z4.D}, P0, [X26, X0,LSL #3]

  (221) 0x420ba8 ADD	X0, X0, X8

  (221) 0x420bac WHILELO	P0.D, X0, X30

  (221) 0x420bb0 B.NE	420b8c

0x420bb4 ADD	W30, W14, W16

0x420bb8 ORR	X17, XZR, X16

0x420bbc CMP	W19, W30

0x420bc0 B.LE	420c00

0x420bc4 SUB	W1, W13, W15

0x420bc8 ORR	W16, WZR, W15

0x420bcc ORR	W15, WZR, W21

0x420bd0 ORR	W2, WZR, W20

0x420bd4 CMP	W1, W15

0x420bd8 CSEL	X30, X1, X15, #9

0x420bdc ADD	W15, W16, W30

0x420be0 CMP	W16, W15

0x420be4 B.CC	420b2c

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp: 64 - 66

--------------------------------------------------------------------------------

64:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

65:         post_vol(i, j) = volume(i, j);

66:         pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.46
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.2]
Source	context.h:69-69,advec_mom.cpp:64-66
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.75
CQA cycles if no scalar integer	6.75
CQA cycles if FP arith vectorized	6.75
CQA cycles if fully vectorized	1.25
Front-end cycles	4.63
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	6.75
P2 cycles	6.75
P3 cycles	6.75
P4 cycles	6.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.67
P10 cycles	2.67
P11 cycles	2.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.48
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	21.71
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.50
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	17.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.46
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.2]
Source	context.h:69-69,advec_mom.cpp:64-66
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.75
CQA cycles if no scalar integer	6.75
CQA cycles if FP arith vectorized	6.75
CQA cycles if fully vectorized	1.25
Front-end cycles	4.63
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	6.75
P2 cycles	6.75
P3 cycles	6.75
P4 cycles	6.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.67
P10 cycles	2.67
P11 cycles	2.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.48
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	21.71
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.50
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	17.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.2]
Source file and lines	advec_mom.cpp:64-66
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:64-66

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 21% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.75 to 1.25 cycles (5.40x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	37
loop length	148
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	6.75	6.75	6.75	6.75	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.00	0.00
cycles	1.00	1.00	6.75	6.75	6.75	6.75	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.63
Overall L1	6.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.75 cycles. At this rate:

9% of peak load performance is reached (9.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 420bc4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X24, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SBFM X23, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X16, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
WHILELO P0.D, XZR, X30	1	0	0	0	0	1	0	0	0	0	3	2
LDR X6, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X18, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X2, X17, X24, X23	1	0	0	0	0	1	0	0	0	0	2	1
LDR X3, [X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X25, X17, X6, X23	1	0	0	0	0	1	0	0	0	0	2	1
LDR X22, [X11, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X26, X17, X18, X23	1	0	0	0	0	1	0	0	0	0	2	1
LDR X7, [X12, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X17, X17, X3, X3	1	0	0	0	0	1	0	0	0	0	2	1
LDR X24, [X9, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X1, X22, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X22, [X10, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB X4, X17, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X5, X17, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X23, X4, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X18, X7, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X6, X7, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X25, X24, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X26, X22, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W30, W14, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X17, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W19, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 420c00 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SUB W1, W13, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W16, WZR, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W15, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W2, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W1, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
CSEL X30, X1, X15, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W15, W16, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W16, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.CC 420b2c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.2]
Source file and lines	advec_mom.cpp:64-66
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_mom.cpp:64-66

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	37
loop length	148
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	6.75	6.75	6.75	6.75	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.00	0.00
cycles	1.00	1.00	6.75	6.75	6.75	6.75	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.63
Overall L1	6.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.75 cycles. At this rate:

9% of peak load performance is reached (9.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 420bc4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X24, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SBFM X23, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X16, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
WHILELO P0.D, XZR, X30	1	0	0	0	0	1	0	0	0	0	3	2
LDR X6, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X18, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X2, X17, X24, X23	1	0	0	0	0	1	0	0	0	0	2	1
LDR X3, [X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X25, X17, X6, X23	1	0	0	0	0	1	0	0	0	0	2	1
LDR X22, [X11, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X26, X17, X18, X23	1	0	0	0	0	1	0	0	0	0	2	1
LDR X7, [X12, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X17, X17, X3, X3	1	0	0	0	0	1	0	0	0	0	2	1
LDR X24, [X9, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X1, X22, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X22, [X10, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB X4, X17, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X5, X17, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X23, X4, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X18, X7, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X6, X7, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X25, X24, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X26, X22, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W30, W14, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X17, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W19, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 420c00 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SUB W1, W13, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W16, WZR, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W15, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W2, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W1, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
CSEL X30, X1, X15, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W15, W16, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W16, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.CC 420b2c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code