OV - exec - Loop 206

    (209) 0x420124 LDR	X23, [X28]

    (209) 0x420128 SBFM	X0, X18, #0, #31

    (209) 0x42012c SUB	W22, W30, #1

    (209) 0x420130 LDP	X9, X8, [SP, #128]

    (209) 0x420134 ADD	X5, X0, #1

    (209) 0x420138 SBFM	X30, X25, #0, #31

    (209) 0x42013c ADD	X12, X5, X22

    (209) 0x420140 LDR	X1, [X27]

    (209) 0x420144 MADD	X7, X13, X23, XZR

    (209) 0x420148 LDR	X2, [X26]

    (209) 0x42014c LDR	X6, [X28, #16]

    (209) 0x420150 MADD	X4, X13, X1, XZR

    (209) 0x420154 LDR	X3, [X27, #16]

    (209) 0x420158 MADD	X20, X13, X2, XZR

    (209) 0x42015c LDR	X10, [SP, #144]

    (209) 0x420160 ADD	X17, X6, X7,LSL #3

    (209) 0x420164 LDR	X16, [SP, #152]

    (209) 0x420168 ADD	X18, X3, X4,LSL #3

    (209) 0x42016c LDR	X21, [X8, #8]

    (209) 0x420170 LDR	X15, [X26, #16]

    (209) 0x420174 LDR	X8, [X10]

    (209) 0x420178 ADD	X23, X21, X13,LSL #3

    (209) 0x42017c LDR	X22, [X9]

    (209) 0x420180 ADD	X20, X15, X20,LSL #3

    (209) 0x420184 LDR	X7, [X16]

    (209) 0x420188 LDR	X4, [X10, #16]

    (209) 0x42018c LDR	X14, [X9, #16]

    (209) 0x420190 LDR	X6, [X16, #16]

    (209) 0x420194 HINT	#0

    (209) 0x420198 HINT	#0

    (209) 0x42019c HINT	#0

    (209) 0x4201a0 ORR	X1, XZR, X11

    (209) 0x4201a4 ORR	X2, XZR, X30

    (209) 0x4201a8 LDR	D6, [X18, X0,LSL #3]

    (209) 0x4201ac ORR	X3, XZR, X13

    (209) 0x4201b0 ORR	X10, XZR, X11

    (209) 0x4201b4 FCMPE	D6, #0

    (209) 0x4201b8 B.GT	4201d4

  (210) 0x4201bc CMP	W24, W19

  (210) 0x4201c0 CSEL	W2, W24, W19, #13

  (210) 0x4201c4 SBFM	X10, X2, #0, #31

  (210) 0x4201c8 ORR	X3, XZR, X11

  (210) 0x4201cc ORR	X1, XZR, X13

  (210) 0x4201d0 ORR	X2, XZR, X10

  (210) 0x4201d4 MADD	X9, X22, X1, X0

  (210) 0x4201d8 FABS	D2, D6

  (210) 0x4201dc LDR	D4, [X21, X10,LSL #3]

  (210) 0x4201e0 MADD	X16, X8, X3, X0

  (210) 0x4201e4 MADD	X10, X8, X1, X0

  (210) 0x4201e8 LDR	D5, [X23]

  (210) 0x4201ec MADD	X15, X8, X2, X0

  (210) 0x4201f0 LDR	D1, [X14, X9,LSL #3]

  (210) 0x4201f4 MADD	X1, X7, X1, X0

  (210) 0x4201f8 MADD	X3, X7, X3, X0

  (210) 0x4201fc LDR	D0, [X4, X10,LSL #3]

  (210) 0x420200 MADD	X2, X7, X2, X0

  (210) 0x420204 LDR	D3, [X4, X16,LSL #3]

  (210) 0x420208 FDIV	D26, D5, D4

  (210) 0x42020c LDR	D19, [X4, X15,LSL #3]

  (210) 0x420210 FDIV	D23, D2, D1

  (210) 0x420214 FSUB	D24, D3, S0

  (210) 0x420218 FSUB	D27, D0, S19

  (210) 0x42021c FCMPE	D24, #0

  (210) 0x420220 FABS	D25, D24

  (210) 0x420224 FMUL	D29, D24, D27

  (210) 0x420228 FABS	D28, D27

  (210) 0x42022c FMINNM	D22, D25, D28

  (210) 0x420230 FCSEL	D20, D16, D7, #9

  (210) 0x420234 FCMPE	D29, #0

  (210) 0x420238 FADD	D30, D23, D7

  (210) 0x42023c FSUB	D21, D7, S23

  (210) 0x420240 FSUB	D31, D18, S23

  (210) 0x420244 FMUL	D24, D26, D30

  (210) 0x420248 B.LS	420264

  (210) 0x42024c FMUL	D2, D25, D31

  (210) 0x420250 FMADD	D4, D28, D24, D2

  (210) 0x420254 FMUL	D1, D4, D17

  (210) 0x420258 FMINNM	D3, D1, D22

  (210) 0x42025c FMUL	D23, D3, D21

  (210) 0x420260 FMADD	D0, D23, D20, D0

  (210) 0x420264 FMUL	D25, D0, D6

  (210) 0x420268 STR	D25, [X17, X0,LSL #3]

  (210) 0x42026c FABS	D6, D25

  (210) 0x420270 LDR	D5, [X6, X1,LSL #3]

  (210) 0x420274 LDR	D21, [X6, X3,LSL #3]

  (210) 0x420278 LDR	D26, [X6, X2,LSL #3]

  (210) 0x42027c LDR	D20, [X4, X10,LSL #3]

  (210) 0x420280 FMUL	D27, D5, D25

  (210) 0x420284 FSUB	D28, D21, S5

  (210) 0x420288 LDR	D22, [X14, X9,LSL #3]

  (210) 0x42028c FSUB	D19, D5, S26

  (210) 0x420290 FABS	D30, D28

  (210) 0x420294 FCMPE	D28, #0

  (210) 0x420298 FMUL	D29, D22, D20

  (210) 0x42029c FMUL	D2, D28, D19

  (210) 0x4202a0 FABS	D4, D19

  (210) 0x4202a4 FMINNM	D23, D30, D4

  (210) 0x4202a8 FMUL	D31, D30, D31

  (210) 0x4202ac FCSEL	D3, D16, D7, #9

  (210) 0x4202b0 FCMPE	D2, #0

  (210) 0x4202b4 FMADD	D24, D4, D24, D31

  (210) 0x4202b8 B.LS	420304

  (210) 0x4202bc FDIV	D0, D6, D29

  (210) 0x4202c0 FMUL	D1, D24, D17

  (210) 0x4202c4 FMINNM	D21, D1, D23

  (210) 0x4202c8 FSUB	D6, D7, S0

  (210) 0x4202cc FMUL	D26, D6, D21

  (210) 0x4202d0 FMADD	D5, D26, D3, D5

  (210) 0x4202d4 FMUL	D25, D5, D25

  (210) 0x4202d8 STR	D25, [X20, X0,LSL #3]

  (210) 0x4202dc ORR	X0, XZR, X5

  (210) 0x4202e0 CMP	X12, X5

  (210) 0x4202e4 B.EQ	420314

  (210) 0x4202e8 ADD	X5, X5, #1

  (210) 0x4202ec B	4201a0

0x420304 STR	D27, [X20, X0,LSL #3]

0x420308 ORR	X0, XZR, X5

0x42030c CMP	X12, X5

0x420310 B.NE	4202e8

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 163 - 202

--------------------------------------------------------------------------------

163:           if (vol_flux_y(i, j) > 0.0) {

[...]

174:           sigmat = std::fabs(vol_flux_y(i, j)) / pre_vol(i, donor);

175:           sigma3 = (1.0 + sigmat) * (vertexdy[j] / vertexdy[dif]);

176:           sigma4 = 2.0 - sigmat;

177:           sigmav = sigmat;

178:           diffuw = density1(i, donor) - density1(i, upwind);

179:           diffdw = density1(i, downwind) - density1(i, donor);

180:           wind = 1.0;

181:           if (diffdw <= 0.0) wind = -1.0;

182:           if (diffuw * diffdw > 0.0) {

183:             limiter = (1.0 - sigmav) * wind *

184:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

185:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

186:           } else {

187:             limiter = 0.0;

188:           }

189:           mass_flux_y(i, j) = vol_flux_y(i, j) * (density1(i, donor) + limiter);

190:           sigmam = std::fabs(mass_flux_y(i, j)) / (density1(i, donor) * pre_vol(i, donor));

191:           diffuw = energy1(i, donor) - energy1(i, upwind);

192:           diffdw = energy1(i, downwind) - energy1(i, donor);

193:           wind = 1.0;

194:           if (diffdw <= 0.0) wind = -1.0;

195:           if (diffuw * diffdw > 0.0) {

196:             limiter = (1.0 - sigmam) * wind *

197:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

198:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

199:           } else {

200:             limiter = 0.0;

201:           }

202:           ener_flux(i, j) = mass_flux_y(i, j) * (energy1(i, donor) + limiter);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.00
Bottlenecks	micro-operation queue, P0, P1, P2, P3, P4, P5, P6, P7, P10, P11,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.6]
Source	advec_cell.cpp:202-202
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	0.50
CQA cycles if no scalar integer	0.50
CQA cycles if FP arith vectorized	0.50
CQA cycles if fully vectorized	0.13
Front-end cycles	0.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	4.00
Nb uops	4.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.00
Bottlenecks	micro-operation queue, P0, P1, P2, P3, P4, P5, P6, P7, P10, P11,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.6]
Source	advec_cell.cpp:202-202
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	0.50
CQA cycles if no scalar integer	0.50
CQA cycles if FP arith vectorized	0.50
CQA cycles if fully vectorized	0.13
Front-end cycles	0.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	4.00
Nb uops	4.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.6]
Source file and lines	advec_cell.cpp:163-202
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:163,174-202

Analyzed code is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:202.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 0.50 to 0.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 8 bytes.

General properties

nb instructions	4
loop length	16
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.00	0.00	0.50	0.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.00	0.00	0.50	0.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	0.50
Overall L1	0.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 0.50 cycles. At this rate:

33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 420124

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
STR D27, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
ORR X0, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP X12, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
B.NE 4202e8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.6]
Source file and lines	advec_cell.cpp:163-202
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:163,174-202

Analyzed code is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:202.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 0.50 to 0.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 8 bytes.

General properties

nb instructions	4
loop length	16
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.00	0.00	0.50	0.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.00	0.00	0.50	0.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	0.50
Overall L1	0.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 0.50 cycles. At this rate:

33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 420124

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
STR D27, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
ORR X0, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP X12, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
B.NE 4202e8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.6+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code