OV - exec - Loop 204

	Loop Id: 204	Module: exec	Source: advec_cell.cpp:71-110 [...]	Coverage: 0.5%

0x41fdd8 SBFM	X0, X18, #0, #31

0x41fddc LDR	X6, [X26]    [7]

0x41fde0 SUB	W15, W14, #1

0x41fde4 ADD	X5, X0, #1

0x41fde8 LDR	X18, [X23]    [4]

0x41fdec ADD	X12, X5, X15

0x41fdf0 LDR	X2, [X25]    [6]

0x41fdf4 MADD	X8, X19, X6, XZR

0x41fdf8 LDR	X16, [X23, #16]    [4]

0x41fdfc MADD	X17, X19, X18, XZR

0x41fe00 LDR	X4, [X25, #16]    [6]

0x41fe04 MADD	X3, X19, X2, XZR

0x41fe08 LDR	X7, [X26, #16]    [7]

0x41fe0c ADD	X18, X16, X17,LSL #3

0x41fe10 LDR	X11, [SP, #120]    [3]

0x41fe14 ADD	X17, X4, X3,LSL #3

0x41fe18 LDR	X1, [X24]    [5]

0x41fe1c ADD	X16, X7, X8,LSL #3

0x41fe20 LDR	X9, [X27]    [8]

0x41fe24 LDR	X10, [X28]    [9]

0x41fe28 MADD	X21, X19, X1, XZR

0x41fe2c LDR	X14, [X11, #8]    [2]

0x41fe30 MADD	X6, X19, X9, XZR

0x41fe34 LDR	X13, [X24, #16]    [5]

0x41fe38 MADD	X7, X19, X10, XZR

0x41fe3c LDR	X8, [X27, #16]    [8]

0x41fe40 LDR	X4, [X28, #16]    [9]

0x41fe44 SUB	W15, W0, #2

0x41fe48 SUB	X2, X0, #1

0x41fe4c LDR	D6, [X17, X0,LSL #3]    [1]

0x41fe50 ORR	X3, XZR, X0

0x41fe54 SBFM	X1, X15, #0, #31

0x41fe58 ADD	W9, W0, #1

0x41fe5c ORR	X11, XZR, X2

0x41fe60 FCMPE	D6, #0

0x41fe64 B.GT	41fe80

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 71 - 110

--------------------------------------------------------------------------------

71:           if (vol_flux_x(i, j) > 0.0) {

[...]

86:           diffuw = density1(donor, j) - density1(upwind, j);

87:           diffdw = density1(downwind, j) - density1(donor, j);

[...]

110:           ener_flux(i, j) = mass_flux_x(i, j) * (energy1(donor, j) + limiter);

Path /

Metric	Value
CQA speedup if no scalar integer	6.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.36
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P4,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source	context.h:46-46,context.h:69-69,advec_cell.cpp:71-71,advec_cell.cpp:86-87,advec_cell.cpp:110-110
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	1.38
Front-end cycles	4.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	4.50
P2 cycles	4.25
P3 cycles	6.00
P4 cycles	4.25
P5 cycles	1.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	36.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.00
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.50
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	20.31
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	6.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.36
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P4,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source	context.h:46-46,context.h:69-69,advec_cell.cpp:71-71,advec_cell.cpp:86-87,advec_cell.cpp:110-110
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	1.38
Front-end cycles	4.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	4.50
P2 cycles	4.25
P3 cycles	6.00
P4 cycles	4.25
P5 cycles	1.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	36.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.00
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.50
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	20.31
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source file and lines	advec_cell.cpp:71-110
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:71,86-87,110

The related source loop is multi-versionned.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 1.00 cycles (6.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 1.37 cycles (4.36x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 120 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.50	4.25	6.00	4.25	1.00	0.00	0.00	0.00	5.00	5.00	5.00	0.00	0.00
cycles	0.50	0.50	4.50	4.25	6.00	4.25	1.00	0.00	0.00	0.00	5.00	5.00	5.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.50
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

20% of peak load performance is reached (20.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41fdd8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P10	P11	P12	Latency	Recip. throughput
SBFM X0, X18, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LDR X6, [X26]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB W15, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X5, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LDR X18, [X23]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X12, X5, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LDR X2, [X25]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X8, X19, X6, XZR	1	0	0	0	0	1	0	0	0	0	0	2	1
LDR X16, [X23, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X17, X19, X18, XZR	1	0	0	0	0	1	0	0	0	0	0	2	1
LDR X4, [X25, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X3, X19, X2, XZR	1	0	0	0	0	1	0	0	0	0	0	2	1
LDR X7, [X26, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X18, X16, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LDR X11, [SP, #120]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X17, X4, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LDR X1, [X24]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X16, X7, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LDR X9, [X27]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X10, [X28]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X21, X19, X1, XZR	1	0	0	0	0	1	0	0	0	0	0	2	1
LDR X14, [X11, #8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X6, X19, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	2	1
LDR X13, [X24, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X7, X19, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	2	1
LDR X8, [X27, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X4, [X28, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB W15, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
SUB X2, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LDR D6, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR X3, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
SBFM X1, X15, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD W9, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ORR X11, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
FCMPE D6, #0	1	0	0	0	0	0	0	1	0	0	0	2	1
B.GT 41fe80 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source file and lines	advec_cell.cpp:71-110
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:71,86-87,110

The related source loop is multi-versionned.
Warnings:

Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 1.00 cycles (6.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 120 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	4.50	4.25	6.00	4.25	1.00	0.00	0.00	0.00	5.00	5.00	5.00	0.00	0.00
cycles	0.50	0.50	4.50	4.25	6.00	4.25	1.00	0.00	0.00	0.00	5.00	5.00	5.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.50
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

20% of peak load performance is reached (20.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41fdd8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P10	P11	P12	Latency	Recip. throughput
SBFM X0, X18, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LDR X6, [X26]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB W15, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD X5, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LDR X18, [X23]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X12, X5, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LDR X2, [X25]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X8, X19, X6, XZR	1	0	0	0	0	1	0	0	0	0	0	2	1
LDR X16, [X23, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X17, X19, X18, XZR	1	0	0	0	0	1	0	0	0	0	0	2	1
LDR X4, [X25, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X3, X19, X2, XZR	1	0	0	0	0	1	0	0	0	0	0	2	1
LDR X7, [X26, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X18, X16, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LDR X11, [SP, #120]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X17, X4, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LDR X1, [X24]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X16, X7, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LDR X9, [X27]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X10, [X28]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X21, X19, X1, XZR	1	0	0	0	0	1	0	0	0	0	0	2	1
LDR X14, [X11, #8]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X6, X19, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	2	1
LDR X13, [X24, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X7, X19, X10, XZR	1	0	0	0	0	1	0	0	0	0	0	2	1
LDR X8, [X27, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X4, [X28, #16]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB W15, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
SUB X2, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LDR D6, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR X3, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
SBFM X1, X15, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD W9, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ORR X11, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
FCMPE D6, #0	1	0	0	0	0	0	0	1	0	0	0	2	1
B.GT 41fe80 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code