OV - exec - Loop 201

    (204) 0x41fdd8 SBFM	X0, X18, #0, #31

    (204) 0x41fddc LDR	X6, [X26]

    (204) 0x41fde0 SUB	W15, W14, #1

    (204) 0x41fde4 ADD	X5, X0, #1

    (204) 0x41fde8 LDR	X18, [X23]

    (204) 0x41fdec ADD	X12, X5, X15

    (204) 0x41fdf0 LDR	X2, [X25]

    (204) 0x41fdf4 MADD	X8, X19, X6, XZR

    (204) 0x41fdf8 LDR	X16, [X23, #16]

    (204) 0x41fdfc MADD	X17, X19, X18, XZR

    (204) 0x41fe00 LDR	X4, [X25, #16]

    (204) 0x41fe04 MADD	X3, X19, X2, XZR

    (204) 0x41fe08 LDR	X7, [X26, #16]

    (204) 0x41fe0c ADD	X18, X16, X17,LSL #3

    (204) 0x41fe10 LDR	X11, [SP, #120]

    (204) 0x41fe14 ADD	X17, X4, X3,LSL #3

    (204) 0x41fe18 LDR	X1, [X24]

    (204) 0x41fe1c ADD	X16, X7, X8,LSL #3

    (204) 0x41fe20 LDR	X9, [X27]

    (204) 0x41fe24 LDR	X10, [X28]

    (204) 0x41fe28 MADD	X21, X19, X1, XZR

    (204) 0x41fe2c LDR	X14, [X11, #8]

    (204) 0x41fe30 MADD	X6, X19, X9, XZR

    (204) 0x41fe34 LDR	X13, [X24, #16]

    (204) 0x41fe38 MADD	X7, X19, X10, XZR

    (204) 0x41fe3c LDR	X8, [X27, #16]

    (204) 0x41fe40 LDR	X4, [X28, #16]

    (204) 0x41fe44 SUB	W15, W0, #2

    (204) 0x41fe48 SUB	X2, X0, #1

    (204) 0x41fe4c LDR	D6, [X17, X0,LSL #3]

    (204) 0x41fe50 ORR	X3, XZR, X0

    (204) 0x41fe54 SBFM	X1, X15, #0, #31

    (204) 0x41fe58 ADD	W9, W0, #1

    (204) 0x41fe5c ORR	X11, XZR, X2

    (204) 0x41fe60 FCMPE	D6, #0

    (204) 0x41fe64 B.GT	41fe80

  (205) 0x41fe68 CMP	W20, W9

  (205) 0x41fe6c CSEL	W1, W20, W9, #13

  (205) 0x41fe70 SBFM	X11, X1, #0, #31

  (205) 0x41fe74 ORR	X3, XZR, X2

  (205) 0x41fe78 ORR	X1, XZR, X11

  (205) 0x41fe7c ORR	X2, XZR, X0

  (205) 0x41fe80 ADD	X9, X21, X2

  (205) 0x41fe84 FABS	D3, D6

  (205) 0x41fe88 ADD	X10, X7, X2

  (205) 0x41fe8c ADD	X15, X7, X3

  (205) 0x41fe90 LDR	D1, [X14, X11,LSL #3]

  (205) 0x41fe94 ADD	X11, X6, X1

  (205) 0x41fe98 ADD	X1, X7, X1

  (205) 0x41fe9c ADD	X2, X6, X2

  (205) 0x41fea0 LDR	D2, [X13, X9,LSL #3]

  (205) 0x41fea4 ADD	X3, X6, X3

  (205) 0x41fea8 LDR	D5, [X14, X0,LSL #3]

  (205) 0x41feac LDR	D0, [X4, X10,LSL #3]

  (205) 0x41feb0 FDIV	D20, D3, D2

  (205) 0x41feb4 LDR	D19, [X4, X15,LSL #3]

  (205) 0x41feb8 LDR	D4, [X4, X1,LSL #3]

  (205) 0x41febc FDIV	D23, D5, D1

  (205) 0x41fec0 FSUB	D21, D19, S0

  (205) 0x41fec4 FSUB	D24, D0, S4

  (205) 0x41fec8 FCMPE	D21, #0

  (205) 0x41fecc FABS	D25, D21

  (205) 0x41fed0 FMUL	D27, D21, D24

  (205) 0x41fed4 FABS	D26, D24

  (205) 0x41fed8 FMINNM	D22, D25, D26

  (205) 0x41fedc FADD	D29, D20, D7

  (205) 0x41fee0 FSUB	D28, D7, S20

  (205) 0x41fee4 FSUB	D30, D18, S20

  (205) 0x41fee8 FCSEL	D31, D16, D7, #9

  (205) 0x41feec FCMPE	D27, #0

  (205) 0x41fef0 FMUL	D5, D23, D29

  (205) 0x41fef4 B.LS	41ff10

  (205) 0x41fef8 FMUL	D3, D25, D30

  (205) 0x41fefc FMADD	D1, D26, D5, D3

  (205) 0x41ff00 FMUL	D2, D1, D17

  (205) 0x41ff04 FMINNM	D20, D2, D22

  (205) 0x41ff08 FMUL	D19, D20, D28

  (205) 0x41ff0c FMADD	D0, D19, D31, D0

  (205) 0x41ff10 FMUL	D24, D0, D6

  (205) 0x41ff14 STR	D24, [X16, X0,LSL #3]

  (205) 0x41ff18 FABS	D6, D24

  (205) 0x41ff1c LDR	D4, [X8, X2,LSL #3]

  (205) 0x41ff20 LDR	D21, [X8, X3,LSL #3]

  (205) 0x41ff24 LDR	D25, [X8, X11,LSL #3]

  (205) 0x41ff28 LDR	D26, [X4, X10,LSL #3]

  (205) 0x41ff2c FMUL	D23, D4, D24

  (205) 0x41ff30 FSUB	D27, D21, S4

  (205) 0x41ff34 LDR	D22, [X13, X9,LSL #3]

  (205) 0x41ff38 FSUB	D28, D4, S25

  (205) 0x41ff3c FABS	D31, D27

  (205) 0x41ff40 FCMPE	D27, #0

  (205) 0x41ff44 FMUL	D29, D22, D26

  (205) 0x41ff48 FMUL	D2, D27, D28

  (205) 0x41ff4c FABS	D20, D28

  (205) 0x41ff50 FMINNM	D19, D31, D20

  (205) 0x41ff54 FMUL	D30, D31, D30

  (205) 0x41ff58 FCSEL	D3, D16, D7, #9

  (205) 0x41ff5c FCMPE	D2, #0

  (205) 0x41ff60 FMADD	D5, D20, D5, D30

  (205) 0x41ff64 B.LS	41ffb4

  (205) 0x41ff68 FDIV	D0, D6, D29

  (205) 0x41ff6c FMUL	D1, D5, D17

  (205) 0x41ff70 FMINNM	D21, D1, D19

  (205) 0x41ff74 FSUB	D6, D7, S0

  (205) 0x41ff78 FMUL	D25, D6, D21

  (205) 0x41ff7c FMADD	D4, D25, D3, D4

  (205) 0x41ff80 FMUL	D24, D4, D24

  (205) 0x41ff84 STR	D24, [X18, X0,LSL #3]

  (205) 0x41ff88 ORR	X0, XZR, X5

  (205) 0x41ff8c CMP	X5, X12

  (205) 0x41ff90 B.EQ	41ffc4

  (205) 0x41ff94 ADD	X5, X5, #1

  (205) 0x41ff98 B	41fe44

0x41ffb4 STR	D23, [X18, X0,LSL #3]

0x41ffb8 ORR	X0, XZR, X5

0x41ffbc CMP	X5, X12

0x41ffc0 B.NE	41ff94

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 71 - 110

--------------------------------------------------------------------------------

71:           if (vol_flux_x(i, j) > 0.0) {

[...]

82:           sigmat = std::fabs(vol_flux_x(i, j)) / pre_vol(donor, j);

83:           sigma3 = (1.0 + sigmat) * (vertexdx[i] / vertexdx[dif]);

84:           sigma4 = 2.0 - sigmat;

85:           sigmav = sigmat;

86:           diffuw = density1(donor, j) - density1(upwind, j);

87:           diffdw = density1(downwind, j) - density1(donor, j);

88:           wind = 1.0;

89:           if (diffdw <= 0.0) wind = -1.0;

90:           if (diffuw * diffdw > 0.0) {

91:             limiter = (1.0 - sigmav) * wind *

92:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

93:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

94:           } else {

95:             limiter = 0.0;

96:           }

97:           mass_flux_x(i, j) = vol_flux_x(i, j) * (density1(donor, j) + limiter);

98:           sigmam = std::fabs(mass_flux_x(i, j)) / (density1(donor, j) * pre_vol(donor, j));

99:           diffuw = energy1(donor, j) - energy1(upwind, j);

100:           diffdw = energy1(downwind, j) - energy1(donor, j);

101:           wind = 1.0;

102:           if (diffdw <= 0.0) wind = -1.0;

103:           if (diffuw * diffdw > 0.0) {

104:             limiter = (1.0 - sigmam) * wind *

105:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

106:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

107:           } else {

108:             limiter = 0.0;

109:           }

110:           ener_flux(i, j) = mass_flux_x(i, j) * (energy1(donor, j) + limiter);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.00
Bottlenecks	micro-operation queue, P0, P1, P2, P3, P4, P5, P6, P7, P10, P11,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source	advec_cell.cpp:110-110
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	0.50
CQA cycles if no scalar integer	0.50
CQA cycles if FP arith vectorized	0.50
CQA cycles if fully vectorized	0.13
Front-end cycles	0.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	4.00
Nb uops	4.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.00
Bottlenecks	micro-operation queue, P0, P1, P2, P3, P4, P5, P6, P7, P10, P11,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source	advec_cell.cpp:110-110
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	0.50
CQA cycles if no scalar integer	0.50
CQA cycles if FP arith vectorized	0.50
CQA cycles if fully vectorized	0.13
Front-end cycles	0.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	4.00
Nb uops	4.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source file and lines	advec_cell.cpp:71-110
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:71,82-110

Analyzed code is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:110.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 0.50 to 0.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 8 bytes.

General properties

nb instructions	4
loop length	16
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.00	0.00	0.50	0.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.00	0.00	0.50	0.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	0.50
Overall L1	0.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 0.50 cycles. At this rate:

33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41fdd8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
STR D23, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
ORR X0, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP X5, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
B.NE 41ff94 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.2]
Source file and lines	advec_cell.cpp:71-110
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:71,82-110

Analyzed code is defined in /home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:110.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 0.50 to 0.12 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 8 bytes.

General properties

nb instructions	4
loop length	16
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.00	0.00	0.50	0.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.50	0.00	0.00	0.50	0.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	0.50
Overall L1	0.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 0.50 cycles. At this rate:

33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41fdd8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
STR D23, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	2	0.50
ORR X0, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP X5, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.33
B.NE 41ff94 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.2+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code