OV - exec - Loop 187

	Loop Id: 187	Module: exec	Source: advec_cell.cpp:119-125 [...]	Coverage: 0.02%

0x41f570 SBFM	X6, X7, #0, #31

0x41f574 LDR	X7, [X11]

0x41f578 MOVZ	X0, #0

0x41f57c ADD	X1, X6, #1

0x41f580 WHILELO	P0.D, XZR, X3

0x41f584 LDR	X24, [X13]

0x41f588 LDR	X5, [X14]

0x41f58c MADD	X27, X9, X7, XZR

0x41f590 LDR	X8, [X11, #16]

0x41f594 MADD	X4, X9, X24, XZR

0x41f598 LDR	X22, [X12]

0x41f59c ADD	X23, X27, X1

0x41f5a0 ADD	X25, X27, X6

0x41f5a4 LDR	X2, [X13, #16]

0x41f5a8 ADD	X26, X8, X25,LSL #3

0x41f5ac LDR	X27, [X14, #16]

0x41f5b0 ADD	X7, X8, X23,LSL #3

0x41f5b4 MADD	X8, X9, X5, XZR

0x41f5b8 MADD	X23, X9, X22, X6

0x41f5bc ADD	X25, X8, X1

0x41f5c0 ADD	X22, X8, X6

0x41f5c4 ADD	X1, X4, X1

0x41f5c8 ADD	X4, X4, X6

0x41f5cc ADD	X8, X27, X22,LSL #3

0x41f5d0 ADD	X24, X27, X25,LSL #3

0x41f5d4 LDR	X22, [X16]

0x41f5d8 ADD	X27, X2, X4,LSL #3

0x41f5dc ADD	X5, X2, X1,LSL #3

0x41f5e0 LDR	X2, [X15]

0x41f5e4 LDR	X25, [X16, #16]

0x41f5e8 MADD	X1, X9, X2, X6

0x41f5ec LDR	X2, [X12, #16]

0x41f5f0 MADD	X6, X9, X22, X6

0x41f5f4 LDR	X22, [X15, #16]

0x41f5f8 ADD	X4, X25, X6,LSL #3

0x41f5fc ADD	X23, X2, X23,LSL #3

0x41f600 ADD	X1, X22, X1,LSL #3

  (185) 0x41f604 LD1D	{Z2.D}, P0/Z, [X23, X0,LSL #3]

  (185) 0x41f608 LD1D	{Z0.D}, P0/Z, [X4, X0,LSL #3]

  (185) 0x41f60c LD1D	{Z1.D}, P0/Z, [X27, X0,LSL #3]

  (185) 0x41f610 LD1D	{Z6.D}, P0/Z, [X5, X0,LSL #3]

  (185) 0x41f614 LD1D	{Z3.D}, P0/Z, [X26, X0,LSL #3]

  (185) 0x41f618 LD1D	{Z16.D}, P0/Z, [X7, X0,LSL #3]

  (185) 0x41f61c LD1D	{Z17.D}, P0/Z, [X1, X0,LSL #3]

  (185) 0x41f620 LD1D	{Z19.D}, P0/Z, [X24, X0,LSL #3]

  (185) 0x41f624 LD1D	{Z21.D}, P0/Z, [X8, X0,LSL #3]

  (185) 0x41f628 FMUL	Z5.D, Z2.D, Z0.D

  (185) 0x41f62c FADD	Z4.D, Z1.D, Z2.D

  (185) 0x41f630 FSUB	Z18.D, Z3.D, Z16.D

  (185) 0x41f634 FSUB	Z7.D, Z4.D, Z6.D

  (185) 0x41f638 FMAD	Z17.D, P1/M, Z5.D, Z18.D

  (185) 0x41f63c FSUB	Z20.D, Z5.D, Z19.D

  (185) 0x41f640 FADD	Z22.D, Z20.D, Z21.D

  (185) 0x41f644 FDIVR	Z7.D, P1/M, Z7.D, Z22.D

  (185) 0x41f648 FDIVR	Z22.D, P1/M, Z22.D, Z17.D

  (185) 0x41f64c ST1D	{Z7.D}, P0, [X4, X0,LSL #3]

  (185) 0x41f650 ST1D	{Z22.D}, P0, [X1, X0,LSL #3]

  (185) 0x41f654 ADD	X0, X0, X10

  (185) 0x41f658 WHILELO	P0.D, X0, X3

  (185) 0x41f65c B.NE	41f604

0x41f660 ADD	X9, X9, #1

0x41f664 ADD	W3, W18, W9

0x41f668 CMP	W19, W3

0x41f66c B.LE	41f6a8

0x41f670 SUB	W3, W17, W30

0x41f674 ORR	W26, WZR, W30

0x41f678 ORR	W30, WZR, W21

0x41f67c ORR	W7, WZR, W20

0x41f680 CMP	W3, W30

0x41f684 CSEL	X3, X3, X30, #9

0x41f688 ADD	W30, W26, W3

0x41f68c CMP	W26, W30

0x41f690 B.CC	41f570

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 119 - 125

--------------------------------------------------------------------------------

119:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

120:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

121:         double post_mass_s = pre_mass_s + mass_flux_x(i, j) - mass_flux_x(i + 1, j + 0);

122:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 1, j + 0)) / post_mass_s;

123:         double advec_vol_s = pre_vol(i, j) + vol_flux_x(i, j) - vol_flux_x(i + 1, j + 0);

124:         density1(i, j) = post_mass_s / advec_vol_s;

125:         energy1(i, j) = post_ener_s;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.97
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.44
Bottlenecks	P2, P3, P4, P5,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.3]
Source	context.h:69-69,advec_cell.cpp:119-119,advec_cell.cpp:122-122,advec_cell.cpp:125-125
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	1.81
Front-end cycles	6.25
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	9.00
P2 cycles	9.00
P3 cycles	9.00
P4 cycles	9.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	50.00
Nb uops	50.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.67
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.77
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.61
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.63

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.97
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.44
Bottlenecks	P2, P3, P4, P5,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.3]
Source	context.h:69-69,advec_cell.cpp:119-119,advec_cell.cpp:122-122,advec_cell.cpp:125-125
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	1.81
Front-end cycles	6.25
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	9.00
P2 cycles	9.00
P3 cycles	9.00
P4 cycles	9.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	50.00
Nb uops	50.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.67
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.77
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.61
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.63

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.3]
Source file and lines	advec_cell.cpp:119-125
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:119-125

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 9.00 to 1.81 cycles (4.97x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 96 bytes.

General properties

nb instructions	50
loop length	200
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	4.00	4.00	4.00	0.00	0.00
cycles	1.00	1.00	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	9.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

11% of peak load performance is reached (10.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f670

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
SBFM X6, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X7, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X1, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
WHILELO P0.D, XZR, X3	1	0	0	0	0	1	0	0	0	0	3	2
LDR X24, [X13]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X5, [X14]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X27, X9, X7, XZR	1	0	0	0	0	1	0	0	0	0	2	1
LDR X8, [X11, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X4, X9, X24, XZR	1	0	0	0	0	1	0	0	0	0	2	1
LDR X22, [X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X23, X27, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X25, X27, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X2, [X13, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X26, X8, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X27, [X14, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X7, X8, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X8, X9, X5, XZR	1	0	0	0	0	1	0	0	0	0	2	1
MADD X23, X9, X22, X6	1	0	0	0	0	1	0	0	0	0	2	1
ADD X25, X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X22, X8, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X1, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X4, X4, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X8, X27, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X24, X27, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X22, [X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X27, X2, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X5, X2, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X2, [X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X25, [X16, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X1, X9, X2, X6	1	0	0	0	0	1	0	0	0	0	2	1
LDR X2, [X12, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X6, X9, X22, X6	1	0	0	0	0	1	0	0	0	0	2	1
LDR X22, [X15, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X4, X25, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X23, X2, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X1, X22, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W3, W18, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W19, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 41f6a8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SUB W3, W17, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W26, WZR, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W30, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W7, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W3, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
CSEL X3, X3, X30, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W30, W26, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W26, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.CC 41f570 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.3]
Source file and lines	advec_cell.cpp:119-125
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:119-125

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 96 bytes.

General properties

nb instructions	50
loop length	200
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	4.00	4.00	4.00	0.00	0.00
cycles	1.00	1.00	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Overall L1	9.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

11% of peak load performance is reached (10.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f670

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
SBFM X6, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X7, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X1, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
WHILELO P0.D, XZR, X3	1	0	0	0	0	1	0	0	0	0	3	2
LDR X24, [X13]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X5, [X14]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X27, X9, X7, XZR	1	0	0	0	0	1	0	0	0	0	2	1
LDR X8, [X11, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X4, X9, X24, XZR	1	0	0	0	0	1	0	0	0	0	2	1
LDR X22, [X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X23, X27, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X25, X27, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X2, [X13, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X26, X8, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X27, [X14, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X7, X8, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X8, X9, X5, XZR	1	0	0	0	0	1	0	0	0	0	2	1
MADD X23, X9, X22, X6	1	0	0	0	0	1	0	0	0	0	2	1
ADD X25, X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X22, X8, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X1, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X4, X4, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X8, X27, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X24, X27, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X22, [X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X27, X2, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X5, X2, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X2, [X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X25, [X16, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X1, X9, X2, X6	1	0	0	0	0	1	0	0	0	0	2	1
LDR X2, [X12, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X6, X9, X22, X6	1	0	0	0	0	1	0	0	0	0	2	1
LDR X22, [X15, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X4, X25, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X23, X2, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X1, X22, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W3, W18, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W19, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 41f6a8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SUB W3, W17, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W26, WZR, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W30, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W7, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W3, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
CSEL X3, X3, X30, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W30, W26, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W26, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.CC 41f570 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code