OV - exec - Loop 178

	Loop Id: 178	Module: exec	Source: advec_cell.cpp:46-48 [...]	Coverage: 0.04%

0x41f1a0 LDR	X24, [X12]

0x41f1a4 SBFM	X22, X8, #0, #31

0x41f1a8 ADD	X18, X30, #1

0x41f1ac ADD	X7, X22, #1

0x41f1b0 MOVZ	X0, #0

0x41f1b4 WHILELO	P0.D, XZR, X25

0x41f1b8 LDR	X3, [X11]

0x41f1bc LDR	X8, [X10]

0x41f1c0 MADD	X2, X30, X24, X24

0x41f1c4 LDR	X6, [X12, #16]

0x41f1c8 MADD	X26, X30, X3, X22

0x41f1cc LDR	X3, [X10, #16]

0x41f1d0 SUB	X1, X2, X24

0x41f1d4 ADD	X4, X2, X22

0x41f1d8 MADD	X23, X30, X8, X22

0x41f1dc ADD	X5, X1, X22

0x41f1e0 LDR	X2, [X13]

0x41f1e4 ADD	X1, X6, X4,LSL #3

0x41f1e8 ADD	X8, X6, X5,LSL #3

0x41f1ec ADD	X24, X3, X23,LSL #3

0x41f1f0 LDR	X3, [X14]

0x41f1f4 LDR	X23, [X13, #16]

0x41f1f8 MADD	X4, X30, X2, XZR

0x41f1fc ADD	X6, X4, X22

0x41f200 ADD	X7, X7, X4

0x41f204 ADD	X5, X23, X7,LSL #3

0x41f208 ADD	X2, X23, X6,LSL #3

0x41f20c MADD	X23, X30, X3, X22

0x41f210 LDR	X30, [X11, #16]

0x41f214 ADD	X22, X30, X26,LSL #3

0x41f218 LDR	X26, [X14, #16]

0x41f21c ADD	X4, X26, X23,LSL #3

  (177) 0x41f220 LD1D	{Z1.D}, P0/Z, [X4, X0,LSL #3]

  (177) 0x41f224 LD1D	{Z0.D}, P0/Z, [X5, X0,LSL #3]

  (177) 0x41f228 LD1D	{Z3.D}, P0/Z, [X2, X0,LSL #3]

  (177) 0x41f22c LD1D	{Z5.D}, P0/Z, [X8, X0,LSL #3]

  (177) 0x41f230 LD1D	{Z2.D}, P0/Z, [X1, X0,LSL #3]

  (177) 0x41f234 FADD	Z4.D, Z0.D, Z1.D

  (177) 0x41f238 FADD	Z6.D, Z5.D, Z3.D

  (177) 0x41f23c FSUB	Z7.D, Z4.D, Z6.D

  (177) 0x41f240 FADD	Z16.D, Z7.D, Z2.D

  (177) 0x41f244 ST1D	{Z16.D}, P0, [X22, X0,LSL #3]

  (177) 0x41f248 LD1D	{Z17.D}, P0/Z, [X2, X0,LSL #3]

  (177) 0x41f24c LD1D	{Z18.D}, P0/Z, [X5, X0,LSL #3]

  (177) 0x41f250 FSUB	Z19.D, Z17.D, Z18.D

  (177) 0x41f254 FADD	Z20.D, Z19.D, Z16.D

  (177) 0x41f258 ST1D	{Z20.D}, P0, [X24, X0,LSL #3]

  (177) 0x41f25c ADD	X0, X0, X9

  (177) 0x41f260 WHILELO	P0.D, X0, X25

  (177) 0x41f264 B.NE	41f220

0x41f268 ADD	W25, W16, W18

0x41f26c ORR	X30, XZR, X18

0x41f270 CMP	W19, W25

0x41f274 B.LE	41f2c0

0x41f278 SUB	W1, W15, W17

0x41f27c ORR	W18, WZR, W17

0x41f280 ORR	W17, WZR, W21

0x41f284 ORR	W8, WZR, W20

0x41f288 CMP	W1, W17

0x41f28c CSEL	X25, X1, X17, #9

0x41f290 ADD	W17, W18, W25

0x41f294 CMP	W18, W17

0x41f298 B.CC	41f1a0

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp: 46 - 48

--------------------------------------------------------------------------------

46:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

47:           pre_vol(i, j) = volume(i, j) + (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j));

48:           post_vol(i, j) = pre_vol(i, j) - (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j));

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47
Bottlenecks	P2, P3, P4, P5,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source	context.h:69-69,advec_cell.cpp:46-48
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.25
CQA cycles if no scalar integer	8.25
CQA cycles if FP arith vectorized	8.25
CQA cycles if fully vectorized	1.63
Front-end cycles	5.63
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	8.25
P2 cycles	8.25
P3 cycles	8.25
P4 cycles	8.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.33
P10 cycles	3.33
P11 cycles	3.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	45.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.70
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.33
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	17.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.08
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47
Bottlenecks	P2, P3, P4, P5,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source	context.h:69-69,advec_cell.cpp:46-48
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.25
CQA cycles if no scalar integer	8.25
CQA cycles if FP arith vectorized	8.25
CQA cycles if fully vectorized	1.63
Front-end cycles	5.63
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	8.25
P2 cycles	8.25
P3 cycles	8.25
P4 cycles	8.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	3.33
P10 cycles	3.33
P11 cycles	3.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	45.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.70
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.33
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	17.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source file and lines	advec_cell.cpp:46-48
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:46-48

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.25 to 1.62 cycles (5.08x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 80 bytes.

General properties

nb instructions	45
loop length	180
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	8.25	8.25	8.25	8.25	0.00	0.00	0.00	0.00	3.33	3.33	3.33	0.00	0.00
cycles	1.00	1.00	8.25	8.25	8.25	8.25	0.00	0.00	0.00	0.00	3.33	3.33	3.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.63
Overall L1	8.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.25 cycles. At this rate:

10% of peak load performance is reached (9.70 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f278

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X24, [X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SBFM X22, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X18, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X7, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
WHILELO P0.D, XZR, X25	1	0	0	0	0	1	0	0	0	0	3	2
LDR X3, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X2, X30, X24, X24	1	0	0	0	0	1	0	0	0	0	2	1
LDR X6, [X12, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X26, X30, X3, X22	1	0	0	0	0	1	0	0	0	0	2	1
LDR X3, [X10, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB X1, X2, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X4, X2, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X23, X30, X8, X22	1	0	0	0	0	1	0	0	0	0	2	1
ADD X5, X1, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X2, [X13]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X1, X6, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X8, X6, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X24, X3, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X3, [X14]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X23, [X13, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X4, X30, X2, XZR	1	0	0	0	0	1	0	0	0	0	2	1
ADD X6, X4, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X7, X7, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X5, X23, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X2, X23, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X23, X30, X3, X22	1	0	0	0	0	1	0	0	0	0	2	1
LDR X30, [X11, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X22, X30, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X26, [X14, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X4, X26, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W25, W16, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X30, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 41f2c0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SUB W1, W15, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W18, WZR, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W17, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W8, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W1, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
CSEL X25, X1, X17, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W17, W18, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W18, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.CC 41f1a0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source file and lines	advec_cell.cpp:46-48
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/advec_cell.cpp:46-48

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 80 bytes.

General properties

nb instructions	45
loop length	180
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	8.25	8.25	8.25	8.25	0.00	0.00	0.00	0.00	3.33	3.33	3.33	0.00	0.00
cycles	1.00	1.00	8.25	8.25	8.25	8.25	0.00	0.00	0.00	0.00	3.33	3.33	3.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.63
Overall L1	8.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.25 cycles. At this rate:

10% of peak load performance is reached (9.70 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f278

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X24, [X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SBFM X22, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X18, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X7, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
WHILELO P0.D, XZR, X25	1	0	0	0	0	1	0	0	0	0	3	2
LDR X3, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X2, X30, X24, X24	1	0	0	0	0	1	0	0	0	0	2	1
LDR X6, [X12, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X26, X30, X3, X22	1	0	0	0	0	1	0	0	0	0	2	1
LDR X3, [X10, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB X1, X2, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X4, X2, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X23, X30, X8, X22	1	0	0	0	0	1	0	0	0	0	2	1
ADD X5, X1, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X2, [X13]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X1, X6, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X8, X6, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X24, X3, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X3, [X14]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X23, [X13, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X4, X30, X2, XZR	1	0	0	0	0	1	0	0	0	0	2	1
ADD X6, X4, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X7, X7, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X5, X23, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X2, X23, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X23, X30, X3, X22	1	0	0	0	0	1	0	0	0	0	2	1
LDR X30, [X11, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X22, X30, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X26, [X14, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X4, X26, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W25, W16, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X30, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 41f2c0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SUB W1, W15, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W18, WZR, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W17, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W8, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W1, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
CSEL X25, X1, X17, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W17, W18, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W18, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.CC 41f1a0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code