OV - exec - Loop 172

	Loop Id: 172	Module: exec	Source: accelerate.cpp:42-53 [...]	Coverage: 0.04%

0x41eb80 LDP	X13, X21, [SP, #136]

0x41eb84 SUB	W2, W30, #1

0x41eb88 SBFM	X1, X23, #0, #31

0x41eb8c SBFM	X6, X2, #0, #31

0x41eb90 ORR	W4, WZR, W4

0x41eb94 WHILELO	P0.D, XZR, X4

0x41eb98 LDP	X19, X5, [SP, #104]

0x41eb9c LDP	X24, X12, [SP, #120]

0x41eba0 LDR	X7, [SP, #160]

0x41eba4 LDR	X16, [SP, #208]

0x41eba8 LDR	X27, [X21]

0x41ebac LDR	X23, [X19]

0x41ebb0 LDR	X10, [X24]

0x41ebb4 MADD	X3, X15, X27, X1

0x41ebb8 LDR	X14, [X7]

0x41ebbc MADD	X8, X6, X23, X1

0x41ebc0 LDR	X24, [X16]

0x41ebc4 UBFM	X27, X3, #61, #60

0x41ebc8 MADD	X9, X23, X15, X1

0x41ebcc MADD	X0, X6, X10, X1

0x41ebd0 LDR	X2, [X5]

0x41ebd4 UBFM	X17, X8, #61, #60

0x41ebd8 MADD	X20, X10, X15, X1

0x41ebdc MADD	X18, X6, X14, X1

0x41ebe0 UBFM	X11, X9, #61, #60

0x41ebe4 SUB	X23, X17, #8

0x41ebe8 MADD	X25, X14, X15, X1

0x41ebec UBFM	X8, X0, #61, #60

0x41ebf0 SUB	X22, X11, #8

0x41ebf4 MADD	X19, X6, X24, X1

0x41ebf8 UBFM	X10, X20, #61, #60

0x41ebfc LDR	X13, [X13]

0x41ec00 MADD	X21, X24, X15, X1

0x41ec04 UBFM	X7, X18, #61, #60

0x41ec08 SUB	X14, X8, #8

0x41ec0c MADD	X3, X6, X2, X1

0x41ec10 LDR	X6, [X12]

0x41ec14 UBFM	X26, X25, #61, #60

0x41ec18 UBFM	X0, X19, #61, #60

0x41ec1c MADD	X5, X2, X15, X1

0x41ec20 LDR	X12, [X16, #16]

0x41ec24 SUB	X25, X0, #8

0x41ec28 UBFM	X9, X21, #61, #60

0x41ec2c LDP	X16, X21, [SP, #104]

0x41ec30 SUB	X20, X9, #8

0x41ec34 MADD	X2, X15, X6, X1

0x41ec38 ADD	X19, X12, X0

0x41ec3c LDR	X0, [SP, #216]

0x41ec40 ADD	X24, X12, X20

0x41ec44 ADD	X18, X12, X9

0x41ec48 ADD	X25, X12, X25

0x41ec4c MADD	X20, X15, X13, X1

0x41ec50 LDR	X9, [X16, #16]

0x41ec54 SUB	X13, X7, #8

0x41ec58 ORR	X6, XZR, X0

0x41ec5c LDR	X0, [X0, #16]

0x41ec60 LDR	X12, [X6]

0x41ec64 ADD	X16, X9, X11

0x41ec68 ADD	X23, X9, X23

0x41ec6c ADD	X17, X9, X17

0x41ec70 ADD	X22, X9, X22

0x41ec74 LDR	X9, [X21, #16]

0x41ec78 SUB	X11, X26, #8

0x41ec7c STP	X0, X5, [SP, #168]

0x41ec80 SUB	X0, X10, #8

0x41ec84 MADD	X21, X15, X12, X1

0x41ec88 LDR	X12, [SP, #120]

0x41ec8c ADD	X3, X9, X3,LSL #3

0x41ec90 LDR	X5, [SP, #152]

0x41ec94 LDR	X6, [X5]

0x41ec98 LDR	X5, [X12, #16]

0x41ec9c MADD	X1, X15, X6, X1

0x41eca0 ADD	X12, X5, X0

0x41eca4 LDR	X0, [SP, #160]

0x41eca8 ADD	X6, X5, X10

0x41ecac ADD	X14, X5, X14

0x41ecb0 ADD	X8, X5, X8

0x41ecb4 SUB	X10, X27, #8

0x41ecb8 LDR	X5, [X0, #16]

0x41ecbc LDR	X0, [SP, #128]

0x41ecc0 ADD	X13, X5, X13

0x41ecc4 ADD	X7, X5, X7

0x41ecc8 ADD	X11, X5, X11

0x41eccc ADD	X5, X5, X26

0x41ecd0 LDR	X26, [SP, #144]

0x41ecd4 LDR	X0, [X0, #16]

0x41ecd8 LDR	X26, [X26, #16]

0x41ecdc STR	X0, [SP, #184]

0x41ece0 LDR	X0, [SP, #176]

0x41ece4 ADD	X10, X26, X10

0x41ece8 ADD	X27, X26, X27

0x41ecec LDR	X26, [SP, #136]

0x41ecf0 ADD	X9, X9, X0,LSL #3

0x41ecf4 LDR	X0, [X26, #16]

0x41ecf8 LDR	X26, [SP, #168]

0x41ecfc STR	X0, [SP, #176]

0x41ed00 LDR	X0, [SP, #184]

0x41ed04 ADD	X21, X26, X21,LSL #3

0x41ed08 LDR	X26, [SP, #152]

0x41ed0c ADD	X2, X0, X2,LSL #3

0x41ed10 LDR	X0, [X26, #16]

0x41ed14 LDR	X26, [SP, #176]

0x41ed18 STR	X0, [SP, #168]

0x41ed1c LDR	X0, [SP, #168]

0x41ed20 ADD	X20, X26, X20,LSL #3

0x41ed24 MOVZ	X26, #0

0x41ed28 ADD	X1, X0, X1,LSL #3

  (170) 0x41ed2c LD1D	{Z2.D}, P0/Z, [X24, X26,LSL #3]

  (170) 0x41ed30 LD1D	{Z5.D}, P0/Z, [X22, X26,LSL #3]

  (170) 0x41ed34 LD1D	{Z4.D}, P0/Z, [X25, X26,LSL #3]

  (170) 0x41ed38 LD1D	{Z17.D}, P0/Z, [X19, X26,LSL #3]

  (170) 0x41ed3c LD1D	{Z7.D}, P0/Z, [X23, X26,LSL #3]

  (170) 0x41ed40 FMUL	Z6.D, Z5.D, Z2.D

  (170) 0x41ed44 FMAD	Z7.D, P1/M, Z4.D, Z6.D

  (170) 0x41ed48 LD1D	{Z18.D}, P0/Z, [X17, X26,LSL #3]

  (170) 0x41ed4c LD1D	{Z19.D}, P0/Z, [X18, X26,LSL #3]

  (170) 0x41ed50 LD1D	{Z22.D}, P0/Z, [X12, X26,LSL #3]

  (170) 0x41ed54 LD1D	{Z23.D}, P0/Z, [X6, X26,LSL #3]

  (170) 0x41ed58 LD1D	{Z26.D}, P0/Z, [X9, X26,LSL #3]

  (170) 0x41ed5c LD1D	{Z27.D}, P0/Z, [X14, X26,LSL #3]

  (170) 0x41ed60 LD1D	{Z29.D}, P0/Z, [X8, X26,LSL #3]

  (170) 0x41ed64 LD1D	{Z30.D}, P0/Z, [X3, X26,LSL #3]

  (170) 0x41ed68 LD1D	{Z0.D}, P0/Z, [X21, X26,LSL #3]

  (170) 0x41ed6c LD1D	{Z21.D}, P0/Z, [X16, X26,LSL #3]

  (170) 0x41ed70 FMUL	Z20.D, Z18.D, Z17.D

  (170) 0x41ed74 FSUB	Z25.D, Z22.D, Z23.D

  (170) 0x41ed78 FMAD	Z21.D, P1/M, Z19.D, Z20.D

  (170) 0x41ed7c FMUL	Z28.D, Z25.D, Z26.D

  (170) 0x41ed80 FADD	Z24.D, Z7.D, Z21.D

  (170) 0x41ed84 FSUB	Z31.D, Z27.D, Z29.D

  (170) 0x41ed88 FDIVR	Z24.D, P1/M, Z24.D, Z16.D

  (170) 0x41ed8c FMAD	Z31.D, P1/M, Z30.D, Z28.D

  (170) 0x41ed90 FMAD	Z31.D, P1/M, Z24.D, Z0.D

  (170) 0x41ed94 ST1D	{Z31.D}, P0, [X2, X26,LSL #3]

  (170) 0x41ed98 LD1D	{Z3.D}, P0/Z, [X8, X26,LSL #3]

  (170) 0x41ed9c LD1D	{Z1.D}, P0/Z, [X6, X26,LSL #3]

  (170) 0x41eda0 LD1D	{Z5.D}, P0/Z, [X27, X26,LSL #3]

  (170) 0x41eda4 LD1D	{Z6.D}, P0/Z, [X14, X26,LSL #3]

  (170) 0x41eda8 LD1D	{Z4.D}, P0/Z, [X12, X26,LSL #3]

  (170) 0x41edac LD1D	{Z17.D}, P0/Z, [X10, X26,LSL #3]

  (170) 0x41edb0 FSUB	Z2.D, Z3.D, Z1.D

  (170) 0x41edb4 FMUL	Z7.D, Z2.D, Z5.D

  (170) 0x41edb8 LD1D	{Z19.D}, P0/Z, [X20, X26,LSL #3]

  (170) 0x41edbc FSUB	Z18.D, Z6.D, Z4.D

  (170) 0x41edc0 FMAD	Z18.D, P1/M, Z17.D, Z7.D

  (170) 0x41edc4 FMAD	Z18.D, P1/M, Z24.D, Z19.D

  (170) 0x41edc8 ST1D	{Z18.D}, P0, [X1, X26,LSL #3]

  (170) 0x41edcc LD1D	{Z20.D}, P0/Z, [X2, X26,LSL #3]

  (170) 0x41edd0 LD1D	{Z21.D}, P0/Z, [X3, X26,LSL #3]

  (170) 0x41edd4 LD1D	{Z22.D}, P0/Z, [X13, X26,LSL #3]

  (170) 0x41edd8 LD1D	{Z23.D}, P0/Z, [X7, X26,LSL #3]

  (170) 0x41eddc LD1D	{Z25.D}, P0/Z, [X9, X26,LSL #3]

  (170) 0x41ede0 LD1D	{Z27.D}, P0/Z, [X11, X26,LSL #3]

  (170) 0x41ede4 FSUB	Z26.D, Z22.D, Z23.D

  (170) 0x41ede8 LD1D	{Z28.D}, P0/Z, [X5, X26,LSL #3]

  (170) 0x41edec FSUB	Z29.D, Z27.D, Z28.D

  (170) 0x41edf0 FMUL	Z30.D, Z29.D, Z25.D

  (170) 0x41edf4 FMAD	Z26.D, P1/M, Z21.D, Z30.D

  (170) 0x41edf8 FMAD	Z26.D, P1/M, Z24.D, Z20.D

  (170) 0x41edfc ST1D	{Z26.D}, P0, [X2, X26,LSL #3]

  (170) 0x41ee00 LD1D	{Z31.D}, P0/Z, [X7, X26,LSL #3]

  (170) 0x41ee04 LD1D	{Z0.D}, P0/Z, [X5, X26,LSL #3]

  (170) 0x41ee08 LD1D	{Z3.D}, P0/Z, [X27, X26,LSL #3]

  (170) 0x41ee0c LD1D	{Z1.D}, P0/Z, [X13, X26,LSL #3]

  (170) 0x41ee10 LD1D	{Z6.D}, P0/Z, [X11, X26,LSL #3]

  (170) 0x41ee14 LD1D	{Z7.D}, P0/Z, [X10, X26,LSL #3]

  (170) 0x41ee18 LD1D	{Z4.D}, P0/Z, [X1, X26,LSL #3]

  (170) 0x41ee1c FSUB	Z5.D, Z31.D, Z0.D

  (170) 0x41ee20 FSUB	Z17.D, Z1.D, Z6.D

  (170) 0x41ee24 FMUL	Z2.D, Z5.D, Z3.D

  (170) 0x41ee28 FMAD	Z17.D, P1/M, Z7.D, Z2.D

  (170) 0x41ee2c FMAD	Z24.D, P1/M, Z17.D, Z4.D

  (170) 0x41ee30 ST1D	{Z24.D}, P0, [X1, X26,LSL #3]

  (170) 0x41ee34 ADD	X26, X26, X28

  (170) 0x41ee38 WHILELO	P0.D, X26, X4

  (170) 0x41ee3c B.NE	41ed2c

0x41ee40 LDR	W4, [SP, #192]

0x41ee44 ADD	W30, W30, #1

0x41ee48 ADD	X15, X15, #1

0x41ee4c CMP	W4, W30

0x41ee50 B.LE	41eea0

0x41ee54 LDR	W24, [SP, #100]

0x41ee58 LDR	W19, [SP, #204]

0x41ee5c LDP	W23, W25, [SP, #196]

0x41ee60 SUB	W7, W19, W24

0x41ee64 CMP	W7, W25

0x41ee68 CSEL	W4, W7, W25, #9

0x41ee6c ADD	W3, W24, W4

0x41ee70 STR	W3, [SP, #100]

0x41ee74 CMP	W24, W3

0x41ee78 B.CC	41eb80

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/accelerate.cpp: 42 - 53

--------------------------------------------------------------------------------

42:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

43:       double stepbymass_s = halfdt / ((density0(i - 1, j - 1) * volume(i - 1, j - 1) + density0(i - 1, j + 0) * volume(i - 1, j + 0) +

44:                                        density0(i, j) * volume(i, j) + density0(i + 0, j - 1) * volume(i + 0, j - 1)) *

45:                                       0.25);

46:       xvel1(i, j) = xvel0(i, j) - stepbymass_s * (xarea(i, j) * (pressure(i, j) - pressure(i - 1, j + 0)) +

47:                                                   xarea(i + 0, j - 1) * (pressure(i + 0, j - 1) - pressure(i - 1, j - 1)));

48:       yvel1(i, j) = yvel0(i, j) - stepbymass_s * (yarea(i, j) * (pressure(i, j) - pressure(i + 0, j - 1)) +

49:                                                   yarea(i - 1, j + 0) * (pressure(i - 1, j + 0) - pressure(i - 1, j - 1)));

50:       xvel1(i, j) = xvel1(i, j) - stepbymass_s * (xarea(i, j) * (viscosity(i, j) - viscosity(i - 1, j + 0)) +

51:                                                   xarea(i + 0, j - 1) * (viscosity(i + 0, j - 1) - viscosity(i - 1, j - 1)));

52:       yvel1(i, j) = yvel1(i, j) - stepbymass_s * (yarea(i, j) * (viscosity(i, j) - viscosity(i + 0, j - 1)) +

53:                                                   yarea(i - 1, j + 0) * (viscosity(i - 1, j + 0) - viscosity(i - 1, j - 1)));

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.65
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	P2, P3, P4, P5,
Function	accelerate_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source	context.h:69-69,accelerate.cpp:42-43,accelerate.cpp:52-52
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.00
CQA cycles if no scalar integer	18.00
CQA cycles if FP arith vectorized	18.00
CQA cycles if fully vectorized	3.19
Front-end cycles	15.25
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	18.00
P2 cycles	18.00
P3 cycles	18.00
P4 cycles	18.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	16.17
P10 cycles	15.83
P11 cycles	16.00
P12 cycles	2.50
P13 cycles	2.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	122.00
Nb uops	122.00
Nb loads	NA
Nb stores	5.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.67
Bytes prefetched	0.00
Bytes loaded	364.00
Bytes stored	44.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.21
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.96
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.65
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	P2, P3, P4, P5,
Function	accelerate_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source	context.h:69-69,accelerate.cpp:42-43,accelerate.cpp:52-52
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.00
CQA cycles if no scalar integer	18.00
CQA cycles if FP arith vectorized	18.00
CQA cycles if fully vectorized	3.19
Front-end cycles	15.25
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	18.00
P2 cycles	18.00
P3 cycles	18.00
P4 cycles	18.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	16.17
P10 cycles	15.83
P11 cycles	16.00
P12 cycles	2.50
P13 cycles	2.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	122.00
Nb uops	122.00
Nb loads	NA
Nb stores	5.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.67
Bytes prefetched	0.00
Bytes loaded	364.00
Bytes stored	44.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.21
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.96
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	accelerate_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source file and lines	accelerate.cpp:42-53
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/accelerate.cpp:42-53

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 18.00 to 3.19 cycles (5.65x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 364 bytes. The binary loop is storing 44 bytes.

General properties

nb instructions	122
loop length	488
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	16.17	15.83	16.00	2.50	2.50
cycles	1.00	1.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	16.17	15.83	16.00	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.25
Overall L1	18.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.00 cycles. At this rate:

21% of peak load performance is reached (20.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.44 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41ee54

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDP X13, X21, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB W2, W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X1, X23, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X6, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR W4, WZR, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
WHILELO P0.D, XZR, X4	1	0	0	0	0	1	0	0	0	0	0	0	3	2
LDP X19, X5, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X12, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X7, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [SP, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X3, X15, X27, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X14, [X7]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X8, X6, X23, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X24, [X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X27, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X9, X23, X15, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
MADD X0, X6, X10, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X2, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X17, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X20, X10, X15, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
MADD X18, X6, X14, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
UBFM X11, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X23, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X25, X14, X15, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
UBFM X8, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X22, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X19, X6, X24, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
UBFM X10, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X13, [X13]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X21, X24, X15, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
UBFM X7, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X14, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X3, X6, X2, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X6, [X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X26, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X0, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X5, X2, X15, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X12, [X16, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X9, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X16, X21, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X20, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X2, X15, X6, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X19, X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [SP, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X24, X12, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X18, X12, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X25, X12, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X20, X15, X13, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X9, [X16, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X13, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X6, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X6]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X23, X9, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X17, X9, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X22, X9, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X9, [X21, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X26, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X0, X5, [SP, #168]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X0, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X21, X15, X12, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X12, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X9, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X12, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X1, X15, X6, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X12, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X5, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, X5, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X5, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X10, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X5, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X5, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X11, X5, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X5, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X26, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X26, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X27, X26, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X26, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X21, X26, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X26, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X0, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [SP, #168]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X26, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X0, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W4, [SP, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W30, W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W4, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 41eea0 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W24, [SP, #100]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W19, [SP, #204]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP W23, W25, [SP, #196]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W7, W19, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W7, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W4, W7, W25, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W24, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W3, [SP, #100]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W24, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 41eb80 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	accelerate_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source file and lines	accelerate.cpp:42-53
Module	exec

The loop is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/accelerate.cpp:42-53

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 364 bytes. The binary loop is storing 44 bytes.

General properties

nb instructions	122
loop length	488
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	16.17	15.83	16.00	2.50	2.50
cycles	1.00	1.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	16.17	15.83	16.00	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.25
Overall L1	18.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.00 cycles. At this rate:

21% of peak load performance is reached (20.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.44 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41ee54

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDP X13, X21, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB W2, W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X1, X23, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X6, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR W4, WZR, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
WHILELO P0.D, XZR, X4	1	0	0	0	0	1	0	0	0	0	0	0	3	2
LDP X19, X5, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X12, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X7, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [SP, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X3, X15, X27, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X14, [X7]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X8, X6, X23, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X24, [X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X27, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X9, X23, X15, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
MADD X0, X6, X10, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X2, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X17, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X20, X10, X15, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
MADD X18, X6, X14, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
UBFM X11, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X23, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X25, X14, X15, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
UBFM X8, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X22, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X19, X6, X24, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
UBFM X10, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X13, [X13]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X21, X24, X15, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
UBFM X7, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X14, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X3, X6, X2, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X6, [X12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X26, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X0, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X5, X2, X15, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X12, [X16, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X25, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X9, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X16, X21, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X20, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X2, X15, X6, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X19, X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [SP, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X24, X12, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X18, X12, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X25, X12, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X20, X15, X13, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X9, [X16, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X13, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X6, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X6]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X23, X9, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X17, X9, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X22, X9, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X9, [X21, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X26, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X0, X5, [SP, #168]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X0, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X21, X15, X12, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X12, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X9, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X12, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X1, X15, X6, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X12, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X5, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, X5, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X5, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X10, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X5, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X5, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X11, X5, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X5, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X26, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X26, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X27, X26, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X26, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X21, X26, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X26, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X0, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [SP, #168]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X26, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X0, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W4, [SP, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W30, W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X15, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W4, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 41eea0 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W24, [SP, #100]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W19, [SP, #204]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP W23, W25, [SP, #196]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W7, W19, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W7, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W4, W7, W25, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W24, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W3, [SP, #100]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W24, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 41eb80 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code