OV - exec - Function viscosity_kernel(int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: viscosity_kernel(int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, ...	Module: exec	Source: viscosity.cpp:36-64 [...]	Coverage: 8.94%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp: 36 - 64

--------------------------------------------------------------------------------

36: #pragma omp parallel for simd collapse(2)

37:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

39:       double ugrad = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) - (xvel0(i, j) + xvel0(i + 0, j + 1));

40:       double vgrad = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) - (yvel0(i, j) + yvel0(i + 1, j + 0));

41:       double div = (celldx[i] * (ugrad) + celldy[j] * (vgrad));

42:       double strain2 = 0.5 * (xvel0(i + 0, j + 1) + xvel0(i + 1, j + 1) - xvel0(i, j) - xvel0(i + 1, j + 0)) / celldy[j] +

43:                        0.5 * (yvel0(i + 1, j + 0) + yvel0(i + 1, j + 1) - yvel0(i, j) - yvel0(i + 0, j + 1)) / celldx[i];

44:       double pgradx = (pressure(i + 1, j + 0) - pressure(i - 1, j + 0)) / (celldx[i] + celldx[i + 1]);

45:       double pgrady = (pressure(i + 0, j + 1) - pressure(i + 0, j - 1)) / (celldy[j] + celldy[j + 2]);

46:       double pgradx2 = pgradx * pgradx;

47:       double pgrady2 = pgrady * pgrady;

48:       double limiter = ((0.5 * (ugrad) / celldx[i]) * pgradx2 + (0.5 * (vgrad) / celldy[j]) * pgrady2 + strain2 * pgradx * pgrady) /

49:                        std::fmax(pgradx2 + pgrady2, g_small);

50:       if ((limiter > 0.0) || (div >= 0.0)) {

51:         viscosity(i, j) = 0.0;

52:       } else {

53:         double dirx = 1.0;

54:         if (pgradx < 0.0) dirx = -1.0;

55:         pgradx = dirx * std::fmax(g_small, std::fabs(pgradx));

56:         double diry = 1.0;

57:         if (pgradx < 0.0) diry = -1.0;

58:         pgrady = diry * std::fmax(g_small, std::fabs(pgrady));

59:         double pgrad = std::sqrt(pgradx * pgradx + pgrady * pgrady);

60:         double xgrad = std::fabs(celldx[i] * pgrad / pgradx);

61:         double ygrad = std::fabs(celldy[j] * pgrad / pgrady);

62:         double grad = std::fmin(xgrad, ygrad);

63:         double grad2 = grad * grad;

64:         viscosity(i, j) = 2.0 * density0(i, j) * grad2 * limiter * limiter;

0x441a40 STP	X29, X30, [SP, #912]!

0x441a44 ADD	X29, SP, #0

0x441a48 STP	X19, X20, [SP, #16]

0x441a4c STP	X25, X26, [SP, #64]

0x441a50 LDP	W25, W20, [X0, #64]

0x441a54 STP	X21, X22, [SP, #32]

0x441a58 ORR	X22, XZR, X0

0x441a5c LDR	W21, [X0, #56]

0x441a60 ADD	W25, W25, #1

0x441a64 ADD	W20, W20, #2

0x441a68 LDR	W0, [X0, #60]

0x441a6c CMP	W25, W20

0x441a70 B.GE	441d3c

0x441a74 ADD	W21, W21, #1

0x441a78 ADD	W19, W0, #2

0x441a7c SUB	W26, W20, W25

0x441a80 CMP	W21, W19

0x441a84 B.GE	441d3c

0x441a88 STP	X23, X24, [SP, #48]

0x441a8c SUB	W24, W19, W21

0x441a90 MADD	W26, W26, W24, WZR

0x441a94 BL	403530

0x441a98 ORR	W23, WZR, W0

0x441a9c BL	4033c0

0x441aa0 UDIV	W2, W26, W23

0x441aa4 ORR	W3, WZR, W0

0x441aa8 MSUB	W1, W2, W23, W26

0x441aac CMP	W0, W1

0x441ab0 B.CC	441d98

0x441ab4 MADD	W3, W2, W3, W1

0x441ab8 ADD	W4, W2, W3

0x441abc STR	W4, [SP, #100]

0x441ac0 CMP	W3, W4

0x441ac4 B.CS	441d50

0x441ac8 UDIV	W9, W3, W24

0x441acc ADRP	X5,

0x441ad0 STP	X27, X28, [SP, #80]

0x441ad4 FMOV	D6, #0.5000000

0x441ad8 MOVI	D7, #0

0x441adc LDR	D5, [X5, #2368]

0x441ae0 LDP	X7, X28, [X22]

0x441ae4 LDP	X15, X27, [X22, #16]

0x441ae8 MSUB	W6, W9, W24, W3

0x441aec ADD	W4, W9, W25

0x441af0 LDP	X26, X25, [X22, #32]

0x441af4 SBFM	X13, X4, #0, #31

0x441af8 ADD	W30, W6, W21

0x441afc STR	X7, [SP, #104]

0x441b00 LDR	X23, [X22, #48]

0x441b04 SUB	W16, W19, W30

  (788) 0x441b08 CMP	W2, W16

  (788) 0x441b0c CSEL	W8, W2, W16, #9

  (788) 0x441b10 ADD	W16, W3, W8

  (788) 0x441b14 ADD	W17, W4, #1

  (788) 0x441b18 CMP	W3, W16

  (788) 0x441b1c B.CS	441d68

  (788) 0x441b20 LDR	X22, [X23]

  (788) 0x441b24 ADD	W14, W30, #1

  (788) 0x441b28 SUB	W10, W4, #1

  (788) 0x441b2c SBFM	X1, X14, #0, #31

  (788) 0x441b30 ADD	W9, W4, #2

  (788) 0x441b34 LDR	X14, [X26]

  (788) 0x441b38 SBFM	X12, X10, #0, #31

  (788) 0x441b3c SBFM	X0, X30, #0, #31

  (788) 0x441b40 SUB	W11, W8, #1

  (788) 0x441b44 ADD	X3, X0, #1

  (788) 0x441b48 LDR	X19, [X23, #16]

  (788) 0x441b4c ADD	X8, X11, X3

  (788) 0x441b50 ADD	X30, X13, #1

  (788) 0x441b54 MADD	X18, X13, X22, X22

  (788) 0x441b58 LDR	X5, [X25]

  (788) 0x441b5c SUB	X2, X18, X22

  (788) 0x441b60 LDR	X7, [X25, #16]

  (788) 0x441b64 ADD	X4, X19, X2,LSL #3

  (788) 0x441b68 ADD	X6, X19, X18,LSL #3

  (788) 0x441b6c LDR	X22, [X26, #16]

  (788) 0x441b70 MADD	X19, X13, X14, XZR

  (788) 0x441b74 LDR	X14, [X27]

  (788) 0x441b78 MADD	X10, X5, X13, XZR

  (788) 0x441b7c ADD	X11, X5, X10

  (788) 0x441b80 ADD	X5, X7, X11,LSL #3

  (788) 0x441b84 MADD	X18, X14, X13, XZR

  (788) 0x441b88 MADD	X12, X12, X14, XZR

  (788) 0x441b8c ADD	X11, X22, X19,LSL #3

  (788) 0x441b90 LDR	X19, [X28, #8]

  (788) 0x441b94 ADD	X9, X19, W9,SXTW #3

  (788) 0x441b98 ADD	X2, X0, X18

  (788) 0x441b9c ADD	X7, X7, X10,LSL #3

  (788) 0x441ba0 SUB	X10, X12, X18

  (788) 0x441ba4 LDR	X22, [X27, #16]

  (788) 0x441ba8 LDR	X18, [SP, #104]

  (788) 0x441bac ADD	X12, X19, X13,LSL #3

  (788) 0x441bb0 ADD	X2, X22, X2,LSL #3

  (788) 0x441bb4 LDR	X18, [X18, #8]

  (788) 0x441bb8 B	441c2c

    (789) 0x441bbc FABS	D20, D29

    (789) 0x441bc0 FMAXNM	D29, D20, D5

    (789) 0x441bc4 FMUL	D25, D29, D31

    (789) 0x441bc8 LDR	X19, [X15]

    (789) 0x441bcc LDR	X22, [X15, #16]

    (789) 0x441bd0 FMUL	D1, D25, D25

    (789) 0x441bd4 MADD	X19, X13, X19, X0

    (789) 0x441bd8 LDR	D3, [X22, X19,LSL #3]

    (789) 0x441bdc FMADD	D0, D21, D21, D1

    (789) 0x441be0 FADD	D23, D3, D3

    (789) 0x441be4 FSQRT	D22, D0

    (789) 0x441be8 FMUL	D4, D22, D4

    (789) 0x441bec FMUL	D18, D22, D18

    (789) 0x441bf0 FDIV	D26, D4, D25

    (789) 0x441bf4 FDIV	D30, D18, D21

    (789) 0x441bf8 FABS	D2, D26

    (789) 0x441bfc FABS	D19, D30

    (789) 0x441c00 FMINNM	D28, D2, D19

    (789) 0x441c04 FMUL	D27, D28, D17

    (789) 0x441c08 FMUL	D16, D27, D27

    (789) 0x441c0c FMUL	D20, D23, D16

    (789) 0x441c10 STR	D20, [X11, X0,LSL #3]

    (789) 0x441c14 ADD	X1, X1, #1

    (789) 0x441c18 ADD	X2, X2, #8

    (789) 0x441c1c ORR	X0, XZR, X3

    (789) 0x441c20 CMP	X3, X8

    (789) 0x441c24 B.EQ	441d70

    (789) 0x441c28 ADD	X3, X3, #1

    (789) 0x441c2c LDR	D21, [X7, X1,LSL #3]

    (789) 0x441c30 MOVI	D20, #0

    (789) 0x441c34 LDR	D24, [X5, X1,LSL #3]

    (789) 0x441c38 LDUR	D3, [X2, #504]

    (789) 0x441c3c LDR	D18, [X18, X0,LSL #3]

    (789) 0x441c40 FADD	D19, D24, D21

    (789) 0x441c44 LDR	D25, [X7, X0,LSL #3]

    (789) 0x441c48 LDR	D2, [X2, X14,LSL #3]

    (789) 0x441c4c LDR	D1, [X2, X10,LSL #3]

    (789) 0x441c50 FDIV	D23, D6, D18

    (789) 0x441c54 LDR	D17, [X18, X1,LSL #3]

    (789) 0x441c58 LDR	D16, [X2, #8]

    (789) 0x441c5c FSUB	D29, D2, S1

    (789) 0x441c60 FSUB	D1, D19, S25

    (789) 0x441c64 LDR	D26, [X5, X0,LSL #3]

    (789) 0x441c68 FADD	D0, D18, D17

    (789) 0x441c6c LDR	D22, [X6, X0,LSL #3]

    (789) 0x441c70 FSUB	D4, D16, S3

    (789) 0x441c74 LDR	D30, [X6, X1,LSL #3]

    (789) 0x441c78 FADD	D2, D26, D24

    (789) 0x441c7c FSUB	D16, D1, S26

    (789) 0x441c80 LDR	D26, [X9]

    (789) 0x441c84 LDR	D28, [X4, X0,LSL #3]

    (789) 0x441c88 FDIV	D31, D4, D0

    (789) 0x441c8c LDR	D4, [X12]

    (789) 0x441c90 FADD	D19, D30, D22

    (789) 0x441c94 FSUB	D17, D2, S25

    (789) 0x441c98 LDR	D27, [X4, X1,LSL #3]

    (789) 0x441c9c FADD	D25, D4, D26

    (789) 0x441ca0 FSUB	D2, D19, S28

    (789) 0x441ca4 FDIV	D24, D6, D4

    (789) 0x441ca8 FADD	D30, D27, D30

    (789) 0x441cac FSUB	D3, D17, S21

    (789) 0x441cb0 FSUB	D27, D2, S27

    (789) 0x441cb4 FDIV	D29, D29, D25

    (789) 0x441cb8 FSUB	D28, D30, S28

    (789) 0x441cbc FABS	D0, D31

    (789) 0x441cc0 FMAXNM	D21, D0, D5

    (789) 0x441cc4 FMUL	D25, D4, D27

    (789) 0x441cc8 FSUB	D1, D28, S22

    (789) 0x441ccc FMUL	D22, D31, D31

    (789) 0x441cd0 FMUL	D30, D1, D23

    (789) 0x441cd4 FMUL	D17, D29, D29

    (789) 0x441cd8 FMUL	D26, D29, D31

    (789) 0x441cdc FMADD	D3, D24, D3, D30

    (789) 0x441ce0 FMUL	D0, D17, D27

    (789) 0x441ce4 FMUL	D27, D22, D16

    (789) 0x441ce8 FMADD	D16, D18, D16, D25

    (789) 0x441cec FADD	D19, D17, D22

    (789) 0x441cf0 FMAXNM	D28, D19, D5

    (789) 0x441cf4 FMUL	D2, D0, D24

    (789) 0x441cf8 FMADD	D23, D27, D23, D2

    (789) 0x441cfc FCMPE	D16, D20

    (789) 0x441d00 FMADD	D24, D26, D3, D23

    (789) 0x441d04 FDIV	D17, D24, D28

    (789) 0x441d08 FCCMPE	D17, D7, #0, #11

    (789) 0x441d0c B.GT	441c10

    (789) 0x441d10 FCMPE	D31, D20

    (789) 0x441d14 FMOV	D31, #1.0000000

    (789) 0x441d18 B.GE	441bbc

    (789) 0x441d1c FCMPE	D21, D20

    (789) 0x441d20 FMOV	D31, #-1.0000000

    (789) 0x441d24 FNEG	D21, D21

    (789) 0x441d28 B.GT	441bbc

    (789) 0x441d2c FMOV	D31, #1.0000000

    (789) 0x441d30 B	441bbc

(786) 0x441d34 LDP	X23, X24, [SP, #48]

(786) 0x441d38 LDP	X27, X28, [SP, #80]

(786) 0x441d3c LDP	X19, X20, [SP, #16]

(786) 0x441d40 LDP	X21, X22, [SP, #32]

(786) 0x441d44 LDP	X25, X26, [SP, #64]

(786) 0x441d48 LDP	X29, X30, [SP], #112

(786) 0x441d4c RET

0x441d50 LDP	X19, X20, [SP, #16]

0x441d54 LDP	X21, X22, [SP, #32]

0x441d58 LDP	X23, X24, [SP, #48]

0x441d5c LDP	X25, X26, [SP, #64]

0x441d60 LDP	X29, X30, [SP], #112

0x441d64 RET

(787) 0x441d68 ORR	W16, WZR, W3

(787) 0x441d6c ADD	X30, X13, #1

  (788) 0x441d70 ORR	X13, XZR, X30

  (788) 0x441d74 CMP	W20, W17

  (788) 0x441d78 B.LE	441d34

  (788) 0x441d7c ORR	W4, WZR, W17

  (788) 0x441d80 LDR	W17, [SP, #100]

  (788) 0x441d84 ORR	W3, WZR, W16

  (788) 0x441d88 ORR	W30, WZR, W21

  (788) 0x441d8c SUB	W2, W17, W16

  (788) 0x441d90 ORR	W16, WZR, W24

  (788) 0x441d94 B	441b08

0x441d98 ADD	W2, W2, #1

0x441d9c MOVZ	W1, #0

0x441da0 B	441ab4

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	viscosity.cpp:36-64
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp:36-64

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.75 to 1.00 cycles (7.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 7.75 to 1.00 cycles (7.75x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.75 to 1.00 cycles (7.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 160 bytes. The binary function is storing 108 bytes.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	7.75	7.75	7.75	7.75	0.50	0.50	0.50	0.50	7.00	7.00	7.00	4.00	4.00
cycles	4.00	4.00	7.75	7.75	7.75	7.75	0.50	0.50	0.50	0.50	7.00	7.00	7.00	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

2.00-1.00

Cycles summary

Front-end	7.38
Overall L1	7.75

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.75 cycles. At this rate:

21% of peak load performance is reached (20.65 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
29% of peak store performance is reached (13.94 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 441a40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W20, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W21, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W20, W20, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W0, [X0, #60]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 441d3c <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W21, W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W19, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W20, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W21, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 441d3c <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W24, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W26, W26, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W23, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W2, W26, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
ORR W3, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB W1, W2, W23, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 441d98 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x358>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W3, W2, W3, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W4, W2, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W4, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W3, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 441d50 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W9, W3, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
ADRP X5, <442acc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FMOV D6, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D5, [X5, #2368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X7, X28, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X15, X27, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MSUB W6, W9, W24, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W4, W9, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X26, X25, [X22, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SBFM X13, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W30, W6, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X7, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X23, [X22, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W16, W19, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W2, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 441ab4 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	viscosity.cpp:36-64
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:46,69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/viscosity.cpp:36-64

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.75 to 1.00 cycles (7.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.75 to 1.00 cycles (7.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 160 bytes. The binary function is storing 108 bytes.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	7.75	7.75	7.75	7.75	0.50	0.50	0.50	0.50	7.00	7.00	7.00	4.00	4.00
cycles	4.00	4.00	7.75	7.75	7.75	7.75	0.50	0.50	0.50	0.50	7.00	7.00	7.00	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

2.00-1.00

Cycles summary

Front-end	7.38
Overall L1	7.75

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.75 cycles. At this rate:

21% of peak load performance is reached (20.65 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
29% of peak store performance is reached (13.94 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 441a40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W25, W20, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W21, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W20, W20, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W0, [X0, #60]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W25, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 441d3c <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W21, W21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W19, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W26, W20, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W21, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 441d3c <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB W24, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD W26, W26, W24, WZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W23, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W2, W26, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
ORR W3, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB W1, W2, W23, W26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 441d98 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x358>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W3, W2, W3, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W4, W2, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W4, [SP, #100]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W3, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 441d50 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV W9, W3, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
ADRP X5, <442acc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FMOV D6, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D5, [X5, #2368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X7, X28, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X15, X27, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MSUB W6, W9, W24, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W4, W9, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X26, X25, [X22, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SBFM X13, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W30, W6, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X7, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X23, [X22, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W16, W19, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W2, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 441ab4 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]–	8.94	2.05
○Loop 786 - viscosity.cpp:36-56 - exec	0	0
▼Loop 787 - viscosity.cpp:38-64 - exec–	0	0
▼Loop 788 - viscosity.cpp:38-64 - exec–	0	0
○Loop 789 - viscosity.cpp:39-64 - exec	8.94	2.05

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code