OV - exec - Function update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> const&, field_type&, int const*, int) [clone ._omp

	Function: update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> c ...	Module: exec	Source: update_halo.cpp:656-659 [...]	Coverage: 0.02%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 656 - 659

--------------------------------------------------------------------------------

656: #pragma omp parallel for simd

657:       for (int j = (x_min - depth + 1); j < (x_max + depth + 2); j++) {

658:         for (int k = 0; k < depth; ++k) {

659:           field.mass_flux_y(j, y_max + k + 1 + 2) = -field.mass_flux_y(j, y_max + 1 - k);

0x435700 STP	X29, X30, [SP, #976]!

0x435704 ADD	X29, SP, #0

0x435708 STP	X19, X20, [SP, #16]

0x43570c LDR	W19, [X0, #8]

0x435710 STP	X21, X22, [SP, #32]

0x435714 ORR	X22, XZR, X0

0x435718 LDR	W20, [X0, #20]

0x43571c SUB	W0, W19, W20

0x435720 ADD	W19, W0, #1

0x435724 BL	403530

0x435728 ORR	W21, WZR, W0

0x43572c BL	4033c0

0x435730 LDR	W2, [X22, #12]

0x435734 ORR	W1, WZR, W0

0x435738 ADD	W3, W20, W2

0x43573c ADD	W4, W3, #2

0x435740 SUB	W5, W4, W19

0x435744 SDIV	W6, W5, W21

0x435748 MSUB	W7, W6, W21, W5

0x43574c CMP	W0, W7

0x435750 B.LT	435964

(591) 0x435754 MADD	W8, W6, W1, W7

(591) 0x435758 ADD	W9, W6, W8

(591) 0x43575c CMP	W8, W9

(591) 0x435760 B.GE	435954

(591) 0x435764 ADD	W10, W19, W8

(591) 0x435768 LDR	W11, [X22, #16]

(591) 0x43576c ADD	W19, W19, W9

(591) 0x435770 LDR	X12, [X22]

(591) 0x435774 CMP	W20, #0

(591) 0x435778 B.LE	435954

(591) 0x43577c ADD	W13, W11, #1

(591) 0x435780 SBFM	X4, X10, #0, #31

(591) 0x435784 LDR	X15, [X12, #336]

(591) 0x435788 SBFM	X14, X13, #0, #31

(591) 0x43578c MOVZ	W30, #0

(591) 0x435790 LDR	X18, [X12, #352]

(591) 0x435794 MADD	X21, X14, X15, XZR

(591) 0x435798 SUB	X0, XZR, X15,LSL #3

(591) 0x43579c ADD	X22, X21, X15,LSL #1

  (593) 0x4357a0 ADD	X16, X4, X21

  (593) 0x4357a4 ADD	X17, X4, X22

  (593) 0x4357a8 ANDS	W5, W20, #128

  (593) 0x4357ac ADD	X1, X18, X16,LSL #3

  (593) 0x4357b0 MOVZ	W3, #0

  (593) 0x4357b4 ADD	X2, X18, X17,LSL #3

  (593) 0x4357b8 B.EQ	43589c

  (593) 0x4357bc CMP	W5, #1

  (593) 0x4357c0 B.EQ	43587c

  (593) 0x4357c4 CMP	W5, #2

  (593) 0x4357c8 B.EQ	435864

  (593) 0x4357cc CMP	W5, #3

  (593) 0x4357d0 B.EQ	43584c

  (593) 0x4357d4 CMP	W5, #4

  (593) 0x4357d8 B.EQ	435834

  (593) 0x4357dc CMP	W5, #5

  (593) 0x4357e0 B.EQ	43581c

  (593) 0x4357e4 CMP	W5, #6

  (593) 0x4357e8 B.EQ	435804

  (593) 0x4357ec LDR	D0, [X18, X16,LSL #3]

  (593) 0x4357f0 ADD	X1, X1, X0

  (593) 0x4357f4 SUB	X2, X2, X0

  (593) 0x4357f8 MOVZ	W3, #1

  (593) 0x4357fc FNEG	D1, D0

  (593) 0x435800 STR	D1, [X18, X17,LSL #3]

  (593) 0x435804 LDR	D2, [X1]

  (593) 0x435808 ADD	W3, W3, #1

  (593) 0x43580c ADD	X1, X1, X0

  (593) 0x435810 FNEG	D3, D2

  (593) 0x435814 STR	D3, [X2]

  (593) 0x435818 SUB	X2, X2, X0

  (593) 0x43581c LDR	D4, [X1]

  (593) 0x435820 ADD	W3, W3, #1

  (593) 0x435824 ADD	X1, X1, X0

  (593) 0x435828 FNEG	D5, D4

  (593) 0x43582c STR	D5, [X2]

  (593) 0x435830 SUB	X2, X2, X0

  (593) 0x435834 LDR	D6, [X1]

  (593) 0x435838 ADD	W3, W3, #1

  (593) 0x43583c ADD	X1, X1, X0

  (593) 0x435840 FNEG	D7, D6

  (593) 0x435844 STR	D7, [X2]

  (593) 0x435848 SUB	X2, X2, X0

  (593) 0x43584c LDR	D16, [X1]

  (593) 0x435850 ADD	W3, W3, #1

  (593) 0x435854 ADD	X1, X1, X0

  (593) 0x435858 FNEG	D17, D16

  (593) 0x43585c STR	D17, [X2]

  (593) 0x435860 SUB	X2, X2, X0

  (593) 0x435864 LDR	D18, [X1]

  (593) 0x435868 ADD	W3, W3, #1

  (593) 0x43586c ADD	X1, X1, X0

  (593) 0x435870 FNEG	D19, D18

  (593) 0x435874 STR	D19, [X2]

  (593) 0x435878 SUB	X2, X2, X0

  (593) 0x43587c LDR	D20, [X1]

  (593) 0x435880 ADD	W3, W3, #1

  (593) 0x435884 ADD	X1, X1, X0

  (593) 0x435888 FNEG	D21, D20

  (593) 0x43588c STR	D21, [X2]

  (593) 0x435890 SUB	X2, X2, X0

  (593) 0x435894 CMP	W20, W3

  (593) 0x435898 B.EQ	435944

    (592) 0x43589c LDR	D22, [X1]

    (592) 0x4358a0 SUB	X17, X2, X0

    (592) 0x4358a4 ADD	X16, X1, X0

    (592) 0x4358a8 SUB	X15, X17, X0

    (592) 0x4358ac ADD	X14, X16, X0

    (592) 0x4358b0 SUB	X13, X15, X0

    (592) 0x4358b4 ADD	X12, X14, X0

    (592) 0x4358b8 SUB	X11, X13, X0

    (592) 0x4358bc ADD	X10, X12, X0

    (592) 0x4358c0 SUB	X9, X11, X0

    (592) 0x4358c4 ADD	X8, X10, X0

    (592) 0x4358c8 SUB	X7, X9, X0

    (592) 0x4358cc ADD	X6, X8, X0

    (592) 0x4358d0 FNEG	D23, D22

    (592) 0x4358d4 SUB	X5, X7, X0

    (592) 0x4358d8 ADD	W3, W3, #8

    (592) 0x4358dc STR	D23, [X2]

    (592) 0x4358e0 SUB	X2, X5, X0

    (592) 0x4358e4 LDR	D24, [X1, X0]

    (592) 0x4358e8 ADD	X1, X6, X0,LSL #1

    (592) 0x4358ec FNEG	D25, D24

    (592) 0x4358f0 STR	D25, [X17]

    (592) 0x4358f4 LDR	D26, [X16, X0]

    (592) 0x4358f8 FNEG	D27, D26

    (592) 0x4358fc STR	D27, [X15]

    (592) 0x435900 LDR	D28, [X14, X0]

    (592) 0x435904 FNEG	D29, D28

    (592) 0x435908 STR	D29, [X13]

    (592) 0x43590c LDR	D30, [X12, X0]

    (592) 0x435910 FNEG	D31, D30

    (592) 0x435914 STR	D31, [X11]

    (592) 0x435918 LDR	D0, [X10, X0]

    (592) 0x43591c FNEG	D1, D0

    (592) 0x435920 STR	D1, [X9]

    (592) 0x435924 LDR	D2, [X8, X0]

    (592) 0x435928 FNEG	D3, D2

    (592) 0x43592c STR	D3, [X7]

    (592) 0x435930 LDR	D4, [X6, X0]

    (592) 0x435934 FNEG	D5, D4

    (592) 0x435938 STR	D5, [X5]

    (592) 0x43593c CMP	W20, W3

    (592) 0x435940 B.NE	43589c

  (593) 0x435944 ADD	X4, X4, #1

  (593) 0x435948 ADD	W3, W30, W4

  (593) 0x43594c CMP	W19, W3

  (593) 0x435950 B.GT	4357a0

(591) 0x435954 LDP	X19, X20, [SP, #16]

(591) 0x435958 LDP	X21, X22, [SP, #32]

(591) 0x43595c LDP	X29, X30, [SP], #48

(591) 0x435960 RET

(591) 0x435964 ADD	W6, W6, #1

(591) 0x435968 MOVZ	W7, #0

(591) 0x43596c B	435754

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:656-659
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:656-659

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.75 to 0.50 cycles (7.50x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 435700

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W20, [X0, #20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W20, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W21, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 435964 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.57+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.cpp:656-659
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:656-659

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 435700

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W20, [X0, #20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W20, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W21, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 435964 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.57+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.57]–	0.02	0
▼Loop 591 - update_halo.cpp:656-659 - exec–	0	0
▼Loop 593 - update_halo.cpp:658-659 - exec–	0.02	0
○Loop 592 - update_halo.cpp:658-659 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code