OV - exec - Function update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> const&, field_type&, int const*, int) [clone ._omp

	Function: update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> c ...	Module: exec	Source: update_halo.cpp:623-626 [...]	Coverage: 0.02%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 623 - 626

--------------------------------------------------------------------------------

623: #pragma omp parallel for simd

624:       for (int k = (y_min - depth + 1); k < (y_max + 1 + depth + 2); k++) {

625:         for (int j = 0; j < depth; ++j) {

626:           field.vol_flux_y(1 - j, k) = field.vol_flux_y(1 + 2 + j, k);

0x435090 STP	X29, X30, [SP, #976]!

0x435094 ADD	X29, SP, #0

0x435098 STP	X19, X20, [SP, #16]

0x43509c LDR	W19, [X0, #8]

0x4350a0 STP	X21, X22, [SP, #32]

0x4350a4 ORR	X22, XZR, X0

0x4350a8 LDR	W21, [X0, #16]

0x4350ac SUB	W0, W19, W21

0x4350b0 ADD	W19, W0, #1

0x4350b4 BL	403530

0x4350b8 ORR	W20, WZR, W0

0x4350bc BL	4033c0

0x4350c0 LDR	W2, [X22, #12]

0x4350c4 ORR	W1, WZR, W0

0x4350c8 ADD	W3, W21, W2

0x4350cc ADD	W4, W3, #3

0x4350d0 SUB	W5, W4, W19

0x4350d4 SDIV	W6, W5, W20

0x4350d8 MSUB	W7, W6, W20, W5

0x4350dc CMP	W0, W7

0x4350e0 B.LT	4352a4

(582) 0x4350e4 MADD	W8, W6, W1, W7

(582) 0x4350e8 ADD	W9, W6, W8

(582) 0x4350ec CMP	W8, W9

(582) 0x4350f0 B.GE	435294

(582) 0x4350f4 ADD	W10, W19, W8

(582) 0x4350f8 ADD	W19, W19, W9

(582) 0x4350fc LDR	X11, [X22]

(582) 0x435100 CMP	W21, #0

(582) 0x435104 B.LE	435294

(582) 0x435108 LDR	X12, [X11, #328]

(582) 0x43510c SBFM	X4, X10, #0, #31

(582) 0x435110 SUB	W21, W21, #1

(582) 0x435114 MOVZ	W15, #0

(582) 0x435118 LDR	X14, [X11, #312]

(582) 0x43511c UBFM	X3, X12, #63, #62

(582) 0x435120 ADD	X13, X12, #8

  (584) 0x435124 MADD	X16, X14, X4, XZR

  (584) 0x435128 ADD	X17, X21, X16

  (584) 0x43512c ADD	X0, X12, X16,LSL #3

  (584) 0x435130 UBFM	X18, X16, #60, #59

  (584) 0x435134 ADD	X5, X13, X17,LSL #3

  (584) 0x435138 ADD	X1, X18, #8

  (584) 0x43513c SUB	X30, X5, X0

  (584) 0x435140 SUB	X22, X30, #8

  (584) 0x435144 UBFM	X20, X22, #3, #63

  (584) 0x435148 ADD	X2, X20, #1

  (584) 0x43514c ANDS	X6, X2, #4224

  (584) 0x435150 B.EQ	4351fc

  (584) 0x435154 CMP	X6, #1

  (584) 0x435158 B.EQ	4351e4

  (584) 0x43515c CMP	X6, #2

  (584) 0x435160 B.EQ	4351d4

  (584) 0x435164 CMP	X6, #3

  (584) 0x435168 B.EQ	4351c4

  (584) 0x43516c CMP	X6, #4

  (584) 0x435170 B.EQ	4351b4

  (584) 0x435174 CMP	X6, #5

  (584) 0x435178 B.EQ	4351a4

  (584) 0x43517c CMP	X6, #6

  (584) 0x435180 B.EQ	435194

  (584) 0x435184 LDR	D0, [X0, #24]

  (584) 0x435188 SUB	X7, X1, X0

  (584) 0x43518c ADD	X0, X0, #8

  (584) 0x435190 STR	D0, [X7, X3]

  (584) 0x435194 LDR	D1, [X0, #24]

  (584) 0x435198 SUB	X8, X1, X0

  (584) 0x43519c ADD	X0, X0, #8

  (584) 0x4351a0 STR	D1, [X8, X3]

  (584) 0x4351a4 LDR	D2, [X0, #24]

  (584) 0x4351a8 SUB	X9, X1, X0

  (584) 0x4351ac ADD	X0, X0, #8

  (584) 0x4351b0 STR	D2, [X9, X3]

  (584) 0x4351b4 LDR	D3, [X0, #24]

  (584) 0x4351b8 SUB	X10, X1, X0

  (584) 0x4351bc ADD	X0, X0, #8

  (584) 0x4351c0 STR	D3, [X10, X3]

  (584) 0x4351c4 LDR	D4, [X0, #24]

  (584) 0x4351c8 SUB	X11, X1, X0

  (584) 0x4351cc ADD	X0, X0, #8

  (584) 0x4351d0 STR	D4, [X11, X3]

  (584) 0x4351d4 LDR	D5, [X0, #24]

  (584) 0x4351d8 SUB	X16, X1, X0

  (584) 0x4351dc ADD	X0, X0, #8

  (584) 0x4351e0 STR	D5, [X16, X3]

  (584) 0x4351e4 LDR	D6, [X0, #24]

  (584) 0x4351e8 SUB	X17, X1, X0

  (584) 0x4351ec ADD	X0, X0, #8

  (584) 0x4351f0 STR	D6, [X17, X3]

  (584) 0x4351f4 CMP	X5, X0

  (584) 0x4351f8 B.EQ	435284

    (583) 0x4351fc LDR	D7, [X0, #24]

    (583) 0x435200 SUB	X6, X1, X0

    (583) 0x435204 ADD	X18, X0, #8

    (583) 0x435208 ADD	X11, X0, #16

    (583) 0x43520c SUB	X30, X1, X18

    (583) 0x435210 ADD	X10, X0, #24

    (583) 0x435214 SUB	X22, X1, X11

    (583) 0x435218 ADD	X9, X0, #32

    (583) 0x43521c SUB	X20, X1, X10

    (583) 0x435220 ADD	X8, X0, #40

    (583) 0x435224 SUB	X18, X1, X9

    (583) 0x435228 ADD	X7, X0, #48

    (583) 0x43522c SUB	X17, X1, X8

    (583) 0x435230 STR	D7, [X6, X3]

    (583) 0x435234 SUB	X16, X1, X7

    (583) 0x435238 ADD	X6, X0, #56

    (583) 0x43523c LDR	D16, [X0, #32]

    (583) 0x435240 SUB	X2, X1, X6

    (583) 0x435244 ADD	X0, X0, #64

    (583) 0x435248 STR	D16, [X30, X3]

    (583) 0x43524c LDR	D17, [X11, #24]

    (583) 0x435250 STR	D17, [X22, X3]

    (583) 0x435254 LDR	D18, [X10, #24]

    (583) 0x435258 STR	D18, [X20, X3]

    (583) 0x43525c LDR	D19, [X9, #24]

    (583) 0x435260 STR	D19, [X18, X3]

    (583) 0x435264 LDR	D20, [X8, #24]

    (583) 0x435268 STR	D20, [X17, X3]

    (583) 0x43526c LDR	D21, [X7, #24]

    (583) 0x435270 STR	D21, [X16, X3]

    (583) 0x435274 LDR	D22, [X6, #24]

    (583) 0x435278 STR	D22, [X2, X3]

    (583) 0x43527c CMP	X5, X0

    (583) 0x435280 B.NE	4351fc

  (584) 0x435284 ADD	X4, X4, #1

  (584) 0x435288 ADD	W5, W15, W4

  (584) 0x43528c CMP	W19, W5

  (584) 0x435290 B.GT	435124

(582) 0x435294 LDP	X19, X20, [SP, #16]

(582) 0x435298 LDP	X21, X22, [SP, #32]

(582) 0x43529c LDP	X29, X30, [SP], #48

(582) 0x4352a0 RET

(582) 0x4352a4 ADD	W6, W6, #1

(582) 0x4352a8 MOVZ	W7, #0

(582) 0x4352ac B	4350e4

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:623-626
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:623-626

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.75 to 0.50 cycles (7.50x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 435090

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4352a4 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.54+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.cpp:623-626
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:623-626

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 435090

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4352a4 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.54+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.54]–	0.02	0
▼Loop 582 - update_halo.cpp:623-626 - exec–	0	0
▼Loop 584 - update_halo.cpp:625-626 - exec–	0.02	0
○Loop 583 - update_halo.cpp:625-626 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code