OV - exec - Function update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> const&, field_type&, int const*, int) [clone ._omp

	Function: update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> c ...	Module: exec	Source: update_halo.cpp:580-583 [...]	Coverage: 0.02%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 580 - 583

--------------------------------------------------------------------------------

580: #pragma omp parallel for simd

581:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

582:         for (int j = 0; j < depth; ++j) {

583:           field.mass_flux_x(1 - j, k) = -field.mass_flux_x(1 + 2 + j, k);

0x434700 STP	X29, X30, [SP, #960]!

0x434704 ADD	X29, SP, #0

0x434708 STP	X19, X20, [SP, #16]

0x43470c LDR	W19, [X0, #8]

0x434710 STP	X21, X22, [SP, #32]

0x434714 ORR	X22, XZR, X0

0x434718 LDR	W21, [X0, #16]

0x43471c SUB	W0, W19, W21

0x434720 ADD	W19, W0, #1

0x434724 BL	403530

0x434728 ORR	W20, WZR, W0

0x43472c BL	4033c0

0x434730 LDR	W2, [X22, #12]

0x434734 ORR	W1, WZR, W0

0x434738 ADD	W3, W21, W2

0x43473c ADD	W4, W3, #2

0x434740 SUB	W5, W4, W19

0x434744 SDIV	W6, W5, W20

0x434748 MSUB	W7, W6, W20, W5

0x43474c CMP	W0, W7

0x434750 B.LT	434964

(570) 0x434754 MADD	W8, W6, W1, W7

(570) 0x434758 ADD	W9, W6, W8

(570) 0x43475c CMP	W8, W9

(570) 0x434760 B.GE	434954

(570) 0x434764 ADD	W10, W19, W8

(570) 0x434768 ADD	W19, W19, W9

(570) 0x43476c LDR	X11, [X22]

(570) 0x434770 CMP	W21, #0

(570) 0x434774 B.LE	434954

(570) 0x434778 LDR	X17, [X11, #304]

(570) 0x43477c SBFM	X4, X10, #0, #31

(570) 0x434780 SUB	W21, W21, #1

(570) 0x434784 MOVZ	W22, #0

(570) 0x434788 LDR	X20, [X11, #288]

(570) 0x43478c UBFM	X3, X17, #63, #62

(570) 0x434790 ADD	X18, X17, #8

(570) 0x434794 HINT	#0

(570) 0x434798 HINT	#0

(570) 0x43479c HINT	#0

  (572) 0x4347a0 MADD	X12, X20, X4, XZR

  (572) 0x4347a4 ADD	X13, X21, X12

  (572) 0x4347a8 ADD	X0, X17, X12,LSL #3

  (572) 0x4347ac UBFM	X14, X12, #60, #59

  (572) 0x4347b0 ADD	X5, X18, X13,LSL #3

  (572) 0x4347b4 ADD	X1, X14, #8

  (572) 0x4347b8 SUB	X15, X5, X0

  (572) 0x4347bc SUB	X16, X15, #8

  (572) 0x4347c0 UBFM	X30, X16, #3, #63

  (572) 0x4347c4 ADD	X2, X30, #1

  (572) 0x4347c8 ANDS	X6, X2, #4224

  (572) 0x4347cc B.EQ	434894

  (572) 0x4347d0 CMP	X6, #1

  (572) 0x4347d4 B.EQ	434878

  (572) 0x4347d8 CMP	X6, #2

  (572) 0x4347dc B.EQ	434864

  (572) 0x4347e0 CMP	X6, #3

  (572) 0x4347e4 B.EQ	434850

  (572) 0x4347e8 CMP	X6, #4

  (572) 0x4347ec B.EQ	43483c

  (572) 0x4347f0 CMP	X6, #5

  (572) 0x4347f4 B.EQ	434828

  (572) 0x4347f8 CMP	X6, #6

  (572) 0x4347fc B.EQ	434814

  (572) 0x434800 LDR	D0, [X0, #24]

  (572) 0x434804 SUB	X7, X1, X0

  (572) 0x434808 ADD	X0, X0, #8

  (572) 0x43480c FNEG	D1, D0

  (572) 0x434810 STR	D1, [X7, X3]

  (572) 0x434814 LDR	D2, [X0, #24]

  (572) 0x434818 SUB	X8, X1, X0

  (572) 0x43481c ADD	X0, X0, #8

  (572) 0x434820 FNEG	D3, D2

  (572) 0x434824 STR	D3, [X8, X3]

  (572) 0x434828 LDR	D4, [X0, #24]

  (572) 0x43482c SUB	X9, X1, X0

  (572) 0x434830 ADD	X0, X0, #8

  (572) 0x434834 FNEG	D5, D4

  (572) 0x434838 STR	D5, [X9, X3]

  (572) 0x43483c LDR	D6, [X0, #24]

  (572) 0x434840 SUB	X10, X1, X0

  (572) 0x434844 ADD	X0, X0, #8

  (572) 0x434848 FNEG	D7, D6

  (572) 0x43484c STR	D7, [X10, X3]

  (572) 0x434850 LDR	D16, [X0, #24]

  (572) 0x434854 SUB	X11, X1, X0

  (572) 0x434858 ADD	X0, X0, #8

  (572) 0x43485c FNEG	D17, D16

  (572) 0x434860 STR	D17, [X11, X3]

  (572) 0x434864 LDR	D18, [X0, #24]

  (572) 0x434868 SUB	X12, X1, X0

  (572) 0x43486c ADD	X0, X0, #8

  (572) 0x434870 FNEG	D19, D18

  (572) 0x434874 STR	D19, [X12, X3]

  (572) 0x434878 LDR	D20, [X0, #24]

  (572) 0x43487c SUB	X13, X1, X0

  (572) 0x434880 ADD	X0, X0, #8

  (572) 0x434884 FNEG	D21, D20

  (572) 0x434888 STR	D21, [X13, X3]

  (572) 0x43488c CMP	X5, X0

  (572) 0x434890 B.EQ	434944

  (572) 0x434894 STP	X23, X24, [SP, #48]

    (571) 0x434898 ADD	X2, X0, #8

    (571) 0x43489c SUB	X24, X1, X0

    (571) 0x4348a0 SUB	X23, X1, X2

    (571) 0x4348a4 ADD	X14, X0, #16

    (571) 0x4348a8 LDR	D22, [X0, #24]

    (571) 0x4348ac ADD	X10, X0, #24

    (571) 0x4348b0 SUB	X30, X1, X14

    (571) 0x4348b4 ADD	X9, X0, #32

    (571) 0x4348b8 SUB	X16, X1, X10

    (571) 0x4348bc ADD	X8, X0, #40

    (571) 0x4348c0 SUB	X15, X1, X9

    (571) 0x4348c4 ADD	X7, X0, #48

    (571) 0x4348c8 SUB	X11, X1, X8

    (571) 0x4348cc ADD	X6, X0, #56

    (571) 0x4348d0 SUB	X13, X1, X7

    (571) 0x4348d4 SUB	X12, X1, X6

    (571) 0x4348d8 ADD	X0, X0, #64

    (571) 0x4348dc FNEG	D23, D22

    (571) 0x4348e0 STR	D23, [X24, X3]

    (571) 0x4348e4 LDR	D24, [X2, #24]

    (571) 0x4348e8 FNEG	D25, D24

    (571) 0x4348ec STR	D25, [X23, X3]

    (571) 0x4348f0 LDR	D26, [X2, #32]

    (571) 0x4348f4 FNEG	D27, D26

    (571) 0x4348f8 STR	D27, [X30, X3]

    (571) 0x4348fc LDR	D28, [X10, #24]

    (571) 0x434900 FNEG	D29, D28

    (571) 0x434904 STR	D29, [X16, X3]

    (571) 0x434908 LDR	D30, [X9, #24]

    (571) 0x43490c FNEG	D31, D30

    (571) 0x434910 STR	D31, [X15, X3]

    (571) 0x434914 LDR	D0, [X8, #24]

    (571) 0x434918 FNEG	D1, D0

    (571) 0x43491c STR	D1, [X11, X3]

    (571) 0x434920 LDR	D2, [X7, #24]

    (571) 0x434924 FNEG	D3, D2

    (571) 0x434928 STR	D3, [X13, X3]

    (571) 0x43492c LDR	D4, [X6, #24]

    (571) 0x434930 FNEG	D5, D4

    (571) 0x434934 STR	D5, [X12, X3]

    (571) 0x434938 CMP	X5, X0

    (571) 0x43493c B.NE	434898

  (572) 0x434940 LDP	X23, X24, [SP, #48]

  (572) 0x434944 ADD	X4, X4, #1

  (572) 0x434948 ADD	W5, W22, W4

  (572) 0x43494c CMP	W19, W5

  (572) 0x434950 B.GT	4347a0

(570) 0x434954 LDP	X19, X20, [SP, #16]

(570) 0x434958 LDP	X21, X22, [SP, #32]

(570) 0x43495c LDP	X29, X30, [SP], #64

(570) 0x434960 RET

(570) 0x434964 ADD	W6, W6, #1

(570) 0x434968 MOVZ	W7, #0

(570) 0x43496c B	434754

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:580-583
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:580-583

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.75 to 0.50 cycles (7.50x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 434700

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #960]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 434964 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.50+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.cpp:580-583
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:580-583

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 434700

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #960]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 434964 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.50+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.50]–	0.02	0
▼Loop 570 - update_halo.cpp:580-583 - exec–	0	0
▼Loop 572 - update_halo.cpp:582-583 - exec–	0.02	0
○Loop 571 - update_halo.cpp:582-583 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code