OV - exec - Function update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> const&, field_type&, int const*, int) [clone ._omp

	Function: update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> c ...	Module: exec	Source: update_halo.cpp:494-497 [...]	Coverage: 0.02%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 494 - 497

--------------------------------------------------------------------------------

494: #pragma omp parallel for simd

495:       for (int k = (y_min - depth + 1); k < (y_max + 1 + depth + 2); k++) {

496:         for (int j = 0; j < depth; ++j) {

497:           field.yvel1(1 - j, k) = field.yvel1(1 + 2 + j, k);

0x433550 STP	X29, X30, [SP, #976]!

0x433554 ADD	X29, SP, #0

0x433558 STP	X19, X20, [SP, #16]

0x43355c LDR	W19, [X0, #8]

0x433560 STP	X21, X22, [SP, #32]

0x433564 ORR	X22, XZR, X0

0x433568 LDR	W21, [X0, #16]

0x43356c SUB	W0, W19, W21

0x433570 ADD	W19, W0, #1

0x433574 BL	403530

0x433578 ORR	W20, WZR, W0

0x43357c BL	4033c0

0x433580 LDR	W2, [X22, #12]

0x433584 ORR	W1, WZR, W0

0x433588 ADD	W3, W21, W2

0x43358c ADD	W4, W3, #3

0x433590 SUB	W5, W4, W19

0x433594 SDIV	W6, W5, W20

0x433598 MSUB	W7, W6, W20, W5

0x43359c CMP	W0, W7

0x4335a0 B.LT	433764

(546) 0x4335a4 MADD	W8, W6, W1, W7

(546) 0x4335a8 ADD	W9, W6, W8

(546) 0x4335ac CMP	W8, W9

(546) 0x4335b0 B.GE	433754

(546) 0x4335b4 ADD	W10, W19, W8

(546) 0x4335b8 ADD	W19, W19, W9

(546) 0x4335bc LDR	X11, [X22]

(546) 0x4335c0 CMP	W21, #0

(546) 0x4335c4 B.LE	433754

(546) 0x4335c8 LDR	X12, [X11, #256]

(546) 0x4335cc SBFM	X4, X10, #0, #31

(546) 0x4335d0 SUB	W21, W21, #1

(546) 0x4335d4 MOVZ	W15, #0

(546) 0x4335d8 LDR	X14, [X11, #240]

(546) 0x4335dc UBFM	X3, X12, #63, #62

(546) 0x4335e0 ADD	X13, X12, #8

  (548) 0x4335e4 MADD	X16, X14, X4, XZR

  (548) 0x4335e8 ADD	X17, X21, X16

  (548) 0x4335ec ADD	X0, X12, X16,LSL #3

  (548) 0x4335f0 UBFM	X18, X16, #60, #59

  (548) 0x4335f4 ADD	X5, X13, X17,LSL #3

  (548) 0x4335f8 ADD	X1, X18, #8

  (548) 0x4335fc SUB	X30, X5, X0

  (548) 0x433600 SUB	X22, X30, #8

  (548) 0x433604 UBFM	X20, X22, #3, #63

  (548) 0x433608 ADD	X2, X20, #1

  (548) 0x43360c ANDS	X6, X2, #4224

  (548) 0x433610 B.EQ	4336bc

  (548) 0x433614 CMP	X6, #1

  (548) 0x433618 B.EQ	4336a4

  (548) 0x43361c CMP	X6, #2

  (548) 0x433620 B.EQ	433694

  (548) 0x433624 CMP	X6, #3

  (548) 0x433628 B.EQ	433684

  (548) 0x43362c CMP	X6, #4

  (548) 0x433630 B.EQ	433674

  (548) 0x433634 CMP	X6, #5

  (548) 0x433638 B.EQ	433664

  (548) 0x43363c CMP	X6, #6

  (548) 0x433640 B.EQ	433654

  (548) 0x433644 LDR	D0, [X0, #24]

  (548) 0x433648 SUB	X7, X1, X0

  (548) 0x43364c ADD	X0, X0, #8

  (548) 0x433650 STR	D0, [X7, X3]

  (548) 0x433654 LDR	D1, [X0, #24]

  (548) 0x433658 SUB	X8, X1, X0

  (548) 0x43365c ADD	X0, X0, #8

  (548) 0x433660 STR	D1, [X8, X3]

  (548) 0x433664 LDR	D2, [X0, #24]

  (548) 0x433668 SUB	X9, X1, X0

  (548) 0x43366c ADD	X0, X0, #8

  (548) 0x433670 STR	D2, [X9, X3]

  (548) 0x433674 LDR	D3, [X0, #24]

  (548) 0x433678 SUB	X10, X1, X0

  (548) 0x43367c ADD	X0, X0, #8

  (548) 0x433680 STR	D3, [X10, X3]

  (548) 0x433684 LDR	D4, [X0, #24]

  (548) 0x433688 SUB	X11, X1, X0

  (548) 0x43368c ADD	X0, X0, #8

  (548) 0x433690 STR	D4, [X11, X3]

  (548) 0x433694 LDR	D5, [X0, #24]

  (548) 0x433698 SUB	X16, X1, X0

  (548) 0x43369c ADD	X0, X0, #8

  (548) 0x4336a0 STR	D5, [X16, X3]

  (548) 0x4336a4 LDR	D6, [X0, #24]

  (548) 0x4336a8 SUB	X17, X1, X0

  (548) 0x4336ac ADD	X0, X0, #8

  (548) 0x4336b0 STR	D6, [X17, X3]

  (548) 0x4336b4 CMP	X5, X0

  (548) 0x4336b8 B.EQ	433744

    (547) 0x4336bc LDR	D7, [X0, #24]

    (547) 0x4336c0 SUB	X6, X1, X0

    (547) 0x4336c4 ADD	X18, X0, #8

    (547) 0x4336c8 ADD	X11, X0, #16

    (547) 0x4336cc SUB	X30, X1, X18

    (547) 0x4336d0 ADD	X10, X0, #24

    (547) 0x4336d4 SUB	X22, X1, X11

    (547) 0x4336d8 ADD	X9, X0, #32

    (547) 0x4336dc SUB	X20, X1, X10

    (547) 0x4336e0 ADD	X8, X0, #40

    (547) 0x4336e4 SUB	X18, X1, X9

    (547) 0x4336e8 ADD	X7, X0, #48

    (547) 0x4336ec SUB	X17, X1, X8

    (547) 0x4336f0 STR	D7, [X6, X3]

    (547) 0x4336f4 SUB	X16, X1, X7

    (547) 0x4336f8 ADD	X6, X0, #56

    (547) 0x4336fc LDR	D16, [X0, #32]

    (547) 0x433700 SUB	X2, X1, X6

    (547) 0x433704 ADD	X0, X0, #64

    (547) 0x433708 STR	D16, [X30, X3]

    (547) 0x43370c LDR	D17, [X11, #24]

    (547) 0x433710 STR	D17, [X22, X3]

    (547) 0x433714 LDR	D18, [X10, #24]

    (547) 0x433718 STR	D18, [X20, X3]

    (547) 0x43371c LDR	D19, [X9, #24]

    (547) 0x433720 STR	D19, [X18, X3]

    (547) 0x433724 LDR	D20, [X8, #24]

    (547) 0x433728 STR	D20, [X17, X3]

    (547) 0x43372c LDR	D21, [X7, #24]

    (547) 0x433730 STR	D21, [X16, X3]

    (547) 0x433734 LDR	D22, [X6, #24]

    (547) 0x433738 STR	D22, [X2, X3]

    (547) 0x43373c CMP	X5, X0

    (547) 0x433740 B.NE	4336bc

  (548) 0x433744 ADD	X4, X4, #1

  (548) 0x433748 ADD	W5, W15, W4

  (548) 0x43374c CMP	W19, W5

  (548) 0x433750 B.GT	4335e4

(546) 0x433754 LDP	X19, X20, [SP, #16]

(546) 0x433758 LDP	X21, X22, [SP, #32]

(546) 0x43375c LDP	X29, X30, [SP], #48

(546) 0x433760 RET

(546) 0x433764 ADD	W6, W6, #1

(546) 0x433768 MOVZ	W7, #0

(546) 0x43376c B	4335a4

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:494-497
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:494-497

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.75 to 0.50 cycles (7.50x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 433550

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 433764 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.42+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.cpp:494-497
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:494-497

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 433550

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 433764 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.42+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.42]–	0.02	0
▼Loop 546 - update_halo.cpp:494-497 - exec–	0	0
▼Loop 548 - update_halo.cpp:496-497 - exec–	0.02	0
○Loop 547 - update_halo.cpp:496-497 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code