OV - exec - Function update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> const&, field_type&, int const*, int) [clone ._omp

	Function: update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> c ...	Module: exec	Source: update_halo.cpp:408-411 [...]	Coverage: 0.04%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 408 - 411

--------------------------------------------------------------------------------

408: #pragma omp parallel for simd

409:       for (int k = (y_min - depth + 1); k < (y_max + 1 + depth + 2); k++) {

410:         for (int j = 0; j < depth; ++j) {

411:           field.xvel1(1 - j, k) = -field.xvel1(1 + 2 + j, k);

0x4322c0 STP	X29, X30, [SP, #960]!

0x4322c4 ADD	X29, SP, #0

0x4322c8 STP	X19, X20, [SP, #16]

0x4322cc LDR	W19, [X0, #8]

0x4322d0 STP	X21, X22, [SP, #32]

0x4322d4 ORR	X22, XZR, X0

0x4322d8 LDR	W21, [X0, #16]

0x4322dc SUB	W0, W19, W21

0x4322e0 ADD	W19, W0, #1

0x4322e4 BL	403530

0x4322e8 ORR	W20, WZR, W0

0x4322ec BL	4033c0

0x4322f0 LDR	W2, [X22, #12]

0x4322f4 ORR	W1, WZR, W0

0x4322f8 ADD	W3, W21, W2

0x4322fc ADD	W4, W3, #3

0x432300 SUB	W5, W4, W19

0x432304 SDIV	W6, W5, W20

0x432308 MSUB	W7, W6, W20, W5

0x43230c CMP	W0, W7

0x432310 B.LT	432524

(522) 0x432314 MADD	W8, W6, W1, W7

(522) 0x432318 ADD	W9, W6, W8

(522) 0x43231c CMP	W8, W9

(522) 0x432320 B.GE	432514

(522) 0x432324 ADD	W10, W19, W8

(522) 0x432328 ADD	W19, W19, W9

(522) 0x43232c LDR	X11, [X22]

(522) 0x432330 CMP	W21, #0

(522) 0x432334 B.LE	432514

(522) 0x432338 LDR	X17, [X11, #208]

(522) 0x43233c SBFM	X4, X10, #0, #31

(522) 0x432340 SUB	W21, W21, #1

(522) 0x432344 MOVZ	W22, #0

(522) 0x432348 LDR	X20, [X11, #192]

(522) 0x43234c UBFM	X3, X17, #63, #62

(522) 0x432350 ADD	X18, X17, #8

(522) 0x432354 HINT	#0

(522) 0x432358 HINT	#0

(522) 0x43235c HINT	#0

  (524) 0x432360 MADD	X12, X20, X4, XZR

  (524) 0x432364 ADD	X13, X21, X12

  (524) 0x432368 ADD	X0, X17, X12,LSL #3

  (524) 0x43236c UBFM	X14, X12, #60, #59

  (524) 0x432370 ADD	X5, X18, X13,LSL #3

  (524) 0x432374 ADD	X1, X14, #8

  (524) 0x432378 SUB	X15, X5, X0

  (524) 0x43237c SUB	X16, X15, #8

  (524) 0x432380 UBFM	X30, X16, #3, #63

  (524) 0x432384 ADD	X2, X30, #1

  (524) 0x432388 ANDS	X6, X2, #4224

  (524) 0x43238c B.EQ	432454

  (524) 0x432390 CMP	X6, #1

  (524) 0x432394 B.EQ	432438

  (524) 0x432398 CMP	X6, #2

  (524) 0x43239c B.EQ	432424

  (524) 0x4323a0 CMP	X6, #3

  (524) 0x4323a4 B.EQ	432410

  (524) 0x4323a8 CMP	X6, #4

  (524) 0x4323ac B.EQ	4323fc

  (524) 0x4323b0 CMP	X6, #5

  (524) 0x4323b4 B.EQ	4323e8

  (524) 0x4323b8 CMP	X6, #6

  (524) 0x4323bc B.EQ	4323d4

  (524) 0x4323c0 LDR	D0, [X0, #24]

  (524) 0x4323c4 SUB	X7, X1, X0

  (524) 0x4323c8 ADD	X0, X0, #8

  (524) 0x4323cc FNEG	D1, D0

  (524) 0x4323d0 STR	D1, [X7, X3]

  (524) 0x4323d4 LDR	D2, [X0, #24]

  (524) 0x4323d8 SUB	X8, X1, X0

  (524) 0x4323dc ADD	X0, X0, #8

  (524) 0x4323e0 FNEG	D3, D2

  (524) 0x4323e4 STR	D3, [X8, X3]

  (524) 0x4323e8 LDR	D4, [X0, #24]

  (524) 0x4323ec SUB	X9, X1, X0

  (524) 0x4323f0 ADD	X0, X0, #8

  (524) 0x4323f4 FNEG	D5, D4

  (524) 0x4323f8 STR	D5, [X9, X3]

  (524) 0x4323fc LDR	D6, [X0, #24]

  (524) 0x432400 SUB	X10, X1, X0

  (524) 0x432404 ADD	X0, X0, #8

  (524) 0x432408 FNEG	D7, D6

  (524) 0x43240c STR	D7, [X10, X3]

  (524) 0x432410 LDR	D16, [X0, #24]

  (524) 0x432414 SUB	X11, X1, X0

  (524) 0x432418 ADD	X0, X0, #8

  (524) 0x43241c FNEG	D17, D16

  (524) 0x432420 STR	D17, [X11, X3]

  (524) 0x432424 LDR	D18, [X0, #24]

  (524) 0x432428 SUB	X12, X1, X0

  (524) 0x43242c ADD	X0, X0, #8

  (524) 0x432430 FNEG	D19, D18

  (524) 0x432434 STR	D19, [X12, X3]

  (524) 0x432438 LDR	D20, [X0, #24]

  (524) 0x43243c SUB	X13, X1, X0

  (524) 0x432440 ADD	X0, X0, #8

  (524) 0x432444 FNEG	D21, D20

  (524) 0x432448 STR	D21, [X13, X3]

  (524) 0x43244c CMP	X5, X0

  (524) 0x432450 B.EQ	432504

  (524) 0x432454 STP	X23, X24, [SP, #48]

    (523) 0x432458 ADD	X2, X0, #8

    (523) 0x43245c SUB	X24, X1, X0

    (523) 0x432460 SUB	X23, X1, X2

    (523) 0x432464 ADD	X14, X0, #16

    (523) 0x432468 LDR	D22, [X0, #24]

    (523) 0x43246c ADD	X10, X0, #24

    (523) 0x432470 SUB	X30, X1, X14

    (523) 0x432474 ADD	X9, X0, #32

    (523) 0x432478 SUB	X16, X1, X10

    (523) 0x43247c ADD	X8, X0, #40

    (523) 0x432480 SUB	X15, X1, X9

    (523) 0x432484 ADD	X7, X0, #48

    (523) 0x432488 SUB	X11, X1, X8

    (523) 0x43248c ADD	X6, X0, #56

    (523) 0x432490 SUB	X13, X1, X7

    (523) 0x432494 SUB	X12, X1, X6

    (523) 0x432498 ADD	X0, X0, #64

    (523) 0x43249c FNEG	D23, D22

    (523) 0x4324a0 STR	D23, [X24, X3]

    (523) 0x4324a4 LDR	D24, [X2, #24]

    (523) 0x4324a8 FNEG	D25, D24

    (523) 0x4324ac STR	D25, [X23, X3]

    (523) 0x4324b0 LDR	D26, [X2, #32]

    (523) 0x4324b4 FNEG	D27, D26

    (523) 0x4324b8 STR	D27, [X30, X3]

    (523) 0x4324bc LDR	D28, [X10, #24]

    (523) 0x4324c0 FNEG	D29, D28

    (523) 0x4324c4 STR	D29, [X16, X3]

    (523) 0x4324c8 LDR	D30, [X9, #24]

    (523) 0x4324cc FNEG	D31, D30

    (523) 0x4324d0 STR	D31, [X15, X3]

    (523) 0x4324d4 LDR	D0, [X8, #24]

    (523) 0x4324d8 FNEG	D1, D0

    (523) 0x4324dc STR	D1, [X11, X3]

    (523) 0x4324e0 LDR	D2, [X7, #24]

    (523) 0x4324e4 FNEG	D3, D2

    (523) 0x4324e8 STR	D3, [X13, X3]

    (523) 0x4324ec LDR	D4, [X6, #24]

    (523) 0x4324f0 FNEG	D5, D4

    (523) 0x4324f4 STR	D5, [X12, X3]

    (523) 0x4324f8 CMP	X5, X0

    (523) 0x4324fc B.NE	432458

  (524) 0x432500 LDP	X23, X24, [SP, #48]

  (524) 0x432504 ADD	X4, X4, #1

  (524) 0x432508 ADD	W5, W22, W4

  (524) 0x43250c CMP	W19, W5

  (524) 0x432510 B.GT	432360

(522) 0x432514 LDP	X19, X20, [SP, #16]

(522) 0x432518 LDP	X21, X22, [SP, #32]

(522) 0x43251c LDP	X29, X30, [SP], #64

(522) 0x432520 RET

(522) 0x432524 ADD	W6, W6, #1

(522) 0x432528 MOVZ	W7, #0

(522) 0x43252c B	432314

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:408-411
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:408-411

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.75 to 0.50 cycles (7.50x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4322c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #960]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 432524 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.34+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.cpp:408-411
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:408-411

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4322c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #960]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 432524 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.34+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.34]–	0.04	0.01
▼Loop 522 - update_halo.cpp:408-411 - exec–	0	0
▼Loop 524 - update_halo.cpp:410-411 - exec–	0.04	0.01
○Loop 523 - update_halo.cpp:410-411 - exec	0	0

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code