OV - exec - Function update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> const&, field_type&, int const*, int) [clone ._omp

	Function: update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> c ...	Module: exec	Source: update_halo.cpp:365-368 [...]	Coverage: 0.09%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 365 - 368

--------------------------------------------------------------------------------

365: #pragma omp parallel for simd

366:       for (int k = (y_min - depth + 1); k < (y_max + 1 + depth + 2); k++) {

367:         for (int j = 0; j < depth; ++j) {

368:           field.xvel0(1 - j, k) = -field.xvel0(1 + 2 + j, k);

0x4319a0 STP	X29, X30, [SP, #960]!

0x4319a4 ADD	X29, SP, #0

0x4319a8 STP	X19, X20, [SP, #16]

0x4319ac LDR	W19, [X0, #8]

0x4319b0 STP	X21, X22, [SP, #32]

0x4319b4 ORR	X22, XZR, X0

0x4319b8 LDR	W21, [X0, #16]

0x4319bc SUB	W0, W19, W21

0x4319c0 ADD	W19, W0, #1

0x4319c4 BL	403530

0x4319c8 ORR	W20, WZR, W0

0x4319cc BL	4033c0

0x4319d0 LDR	W2, [X22, #12]

0x4319d4 ORR	W1, WZR, W0

0x4319d8 ADD	W3, W21, W2

0x4319dc ADD	W4, W3, #3

0x4319e0 SUB	W5, W4, W19

0x4319e4 SDIV	W6, W5, W20

0x4319e8 MSUB	W7, W6, W20, W5

0x4319ec CMP	W0, W7

0x4319f0 B.LT	431c04

(510) 0x4319f4 MADD	W8, W6, W1, W7

(510) 0x4319f8 ADD	W9, W6, W8

(510) 0x4319fc CMP	W8, W9

(510) 0x431a00 B.GE	431bf4

(510) 0x431a04 ADD	W10, W19, W8

(510) 0x431a08 ADD	W19, W19, W9

(510) 0x431a0c LDR	X11, [X22]

(510) 0x431a10 CMP	W21, #0

(510) 0x431a14 B.LE	431bf4

(510) 0x431a18 LDR	X17, [X11, #184]

(510) 0x431a1c SBFM	X4, X10, #0, #31

(510) 0x431a20 SUB	W21, W21, #1

(510) 0x431a24 MOVZ	W22, #0

(510) 0x431a28 LDR	X20, [X11, #168]

(510) 0x431a2c UBFM	X3, X17, #63, #62

(510) 0x431a30 ADD	X18, X17, #8

(510) 0x431a34 HINT	#0

(510) 0x431a38 HINT	#0

(510) 0x431a3c HINT	#0

  (512) 0x431a40 MADD	X12, X20, X4, XZR

  (512) 0x431a44 ADD	X13, X21, X12

  (512) 0x431a48 ADD	X0, X17, X12,LSL #3

  (512) 0x431a4c UBFM	X14, X12, #60, #59

  (512) 0x431a50 ADD	X5, X18, X13,LSL #3

  (512) 0x431a54 ADD	X1, X14, #8

  (512) 0x431a58 SUB	X15, X5, X0

  (512) 0x431a5c SUB	X16, X15, #8

  (512) 0x431a60 UBFM	X30, X16, #3, #63

  (512) 0x431a64 ADD	X2, X30, #1

  (512) 0x431a68 ANDS	X6, X2, #4224

  (512) 0x431a6c B.EQ	431b34

  (512) 0x431a70 CMP	X6, #1

  (512) 0x431a74 B.EQ	431b18

  (512) 0x431a78 CMP	X6, #2

  (512) 0x431a7c B.EQ	431b04

  (512) 0x431a80 CMP	X6, #3

  (512) 0x431a84 B.EQ	431af0

  (512) 0x431a88 CMP	X6, #4

  (512) 0x431a8c B.EQ	431adc

  (512) 0x431a90 CMP	X6, #5

  (512) 0x431a94 B.EQ	431ac8

  (512) 0x431a98 CMP	X6, #6

  (512) 0x431a9c B.EQ	431ab4

  (512) 0x431aa0 LDR	D0, [X0, #24]

  (512) 0x431aa4 SUB	X7, X1, X0

  (512) 0x431aa8 ADD	X0, X0, #8

  (512) 0x431aac FNEG	D1, D0

  (512) 0x431ab0 STR	D1, [X7, X3]

  (512) 0x431ab4 LDR	D2, [X0, #24]

  (512) 0x431ab8 SUB	X8, X1, X0

  (512) 0x431abc ADD	X0, X0, #8

  (512) 0x431ac0 FNEG	D3, D2

  (512) 0x431ac4 STR	D3, [X8, X3]

  (512) 0x431ac8 LDR	D4, [X0, #24]

  (512) 0x431acc SUB	X9, X1, X0

  (512) 0x431ad0 ADD	X0, X0, #8

  (512) 0x431ad4 FNEG	D5, D4

  (512) 0x431ad8 STR	D5, [X9, X3]

  (512) 0x431adc LDR	D6, [X0, #24]

  (512) 0x431ae0 SUB	X10, X1, X0

  (512) 0x431ae4 ADD	X0, X0, #8

  (512) 0x431ae8 FNEG	D7, D6

  (512) 0x431aec STR	D7, [X10, X3]

  (512) 0x431af0 LDR	D16, [X0, #24]

  (512) 0x431af4 SUB	X11, X1, X0

  (512) 0x431af8 ADD	X0, X0, #8

  (512) 0x431afc FNEG	D17, D16

  (512) 0x431b00 STR	D17, [X11, X3]

  (512) 0x431b04 LDR	D18, [X0, #24]

  (512) 0x431b08 SUB	X12, X1, X0

  (512) 0x431b0c ADD	X0, X0, #8

  (512) 0x431b10 FNEG	D19, D18

  (512) 0x431b14 STR	D19, [X12, X3]

  (512) 0x431b18 LDR	D20, [X0, #24]

  (512) 0x431b1c SUB	X13, X1, X0

  (512) 0x431b20 ADD	X0, X0, #8

  (512) 0x431b24 FNEG	D21, D20

  (512) 0x431b28 STR	D21, [X13, X3]

  (512) 0x431b2c CMP	X5, X0

  (512) 0x431b30 B.EQ	431be4

  (512) 0x431b34 STP	X23, X24, [SP, #48]

    (511) 0x431b38 ADD	X2, X0, #8

    (511) 0x431b3c SUB	X24, X1, X0

    (511) 0x431b40 SUB	X23, X1, X2

    (511) 0x431b44 ADD	X14, X0, #16

    (511) 0x431b48 LDR	D22, [X0, #24]

    (511) 0x431b4c ADD	X10, X0, #24

    (511) 0x431b50 SUB	X30, X1, X14

    (511) 0x431b54 ADD	X9, X0, #32

    (511) 0x431b58 SUB	X16, X1, X10

    (511) 0x431b5c ADD	X8, X0, #40

    (511) 0x431b60 SUB	X15, X1, X9

    (511) 0x431b64 ADD	X7, X0, #48

    (511) 0x431b68 SUB	X11, X1, X8

    (511) 0x431b6c ADD	X6, X0, #56

    (511) 0x431b70 SUB	X13, X1, X7

    (511) 0x431b74 SUB	X12, X1, X6

    (511) 0x431b78 ADD	X0, X0, #64

    (511) 0x431b7c FNEG	D23, D22

    (511) 0x431b80 STR	D23, [X24, X3]

    (511) 0x431b84 LDR	D24, [X2, #24]

    (511) 0x431b88 FNEG	D25, D24

    (511) 0x431b8c STR	D25, [X23, X3]

    (511) 0x431b90 LDR	D26, [X2, #32]

    (511) 0x431b94 FNEG	D27, D26

    (511) 0x431b98 STR	D27, [X30, X3]

    (511) 0x431b9c LDR	D28, [X10, #24]

    (511) 0x431ba0 FNEG	D29, D28

    (511) 0x431ba4 STR	D29, [X16, X3]

    (511) 0x431ba8 LDR	D30, [X9, #24]

    (511) 0x431bac FNEG	D31, D30

    (511) 0x431bb0 STR	D31, [X15, X3]

    (511) 0x431bb4 LDR	D0, [X8, #24]

    (511) 0x431bb8 FNEG	D1, D0

    (511) 0x431bbc STR	D1, [X11, X3]

    (511) 0x431bc0 LDR	D2, [X7, #24]

    (511) 0x431bc4 FNEG	D3, D2

    (511) 0x431bc8 STR	D3, [X13, X3]

    (511) 0x431bcc LDR	D4, [X6, #24]

    (511) 0x431bd0 FNEG	D5, D4

    (511) 0x431bd4 STR	D5, [X12, X3]

    (511) 0x431bd8 CMP	X5, X0

    (511) 0x431bdc B.NE	431b38

  (512) 0x431be0 LDP	X23, X24, [SP, #48]

  (512) 0x431be4 ADD	X4, X4, #1

  (512) 0x431be8 ADD	W5, W22, W4

  (512) 0x431bec CMP	W19, W5

  (512) 0x431bf0 B.GT	431a40

(510) 0x431bf4 LDP	X19, X20, [SP, #16]

(510) 0x431bf8 LDP	X21, X22, [SP, #32]

(510) 0x431bfc LDP	X29, X30, [SP], #64

(510) 0x431c00 RET

(510) 0x431c04 ADD	W6, W6, #1

(510) 0x431c08 MOVZ	W7, #0

(510) 0x431c0c B	4319f4

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:365-368
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:365-368

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.75 to 0.50 cycles (7.50x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4319a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #960]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 431c04 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.30+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.cpp:365-368
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:365-368

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4319a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #960]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 431c04 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.30+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.30]–	0.09	0.02
▼Loop 510 - update_halo.cpp:365-368 - exec–	0	0
▼Loop 512 - update_halo.cpp:367-368 - exec–	0.09	0.02
○Loop 511 - update_halo.cpp:367-368 - exec	0	0

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Vectorization

Details

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code