OV - exec - Function update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> const&, field_type&, int const*, int) [clone ._omp

	Function: update_halo_kernel(int, int, int, int, std::array<int, 4ul> const&, std::array<int, 4ul> c ...	Module: exec	Source: update_halo.cpp:279-282 [...]	Coverage: 0.04%

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp: 279 - 282

--------------------------------------------------------------------------------

279: #pragma omp parallel for simd

280:       for (int k = (y_min - depth + 1); k < (y_max + depth + 2); k++) {

281:         for (int j = 0; j < depth; ++j) {

282:           field.viscosity(1 - j, k) = field.viscosity(2 + j, k);

0x430860 STP	X29, X30, [SP, #976]!

0x430864 ADD	X29, SP, #0

0x430868 STP	X19, X20, [SP, #16]

0x43086c LDR	W19, [X0, #8]

0x430870 STP	X21, X22, [SP, #32]

0x430874 ORR	X22, XZR, X0

0x430878 LDR	W21, [X0, #16]

0x43087c SUB	W0, W19, W21

0x430880 ADD	W19, W0, #1

0x430884 BL	403530

0x430888 ORR	W20, WZR, W0

0x43088c BL	4033c0

0x430890 LDR	W2, [X22, #12]

0x430894 ORR	W1, WZR, W0

0x430898 ADD	W3, W21, W2

0x43089c ADD	W4, W3, #2

0x4308a0 SUB	W5, W4, W19

0x4308a4 SDIV	W6, W5, W20

0x4308a8 MSUB	W7, W6, W20, W5

0x4308ac CMP	W0, W7

0x4308b0 B.LT	430a80

(486) 0x4308b4 MADD	W8, W6, W1, W7

(486) 0x4308b8 ADD	W9, W6, W8

(486) 0x4308bc CMP	W8, W9

(486) 0x4308c0 B.GE	430a70

(486) 0x4308c4 ADD	W10, W19, W8

(486) 0x4308c8 ADD	W19, W19, W9

(486) 0x4308cc LDR	X11, [X22]

(486) 0x4308d0 CMP	W21, #0

(486) 0x4308d4 B.LE	430a70

(486) 0x4308d8 LDR	X12, [X11, #136]

(486) 0x4308dc SBFM	X4, X10, #0, #31

(486) 0x4308e0 SUB	W21, W21, #1

(486) 0x4308e4 MOVZ	W15, #0

(486) 0x4308e8 LDR	X14, [X11, #120]

(486) 0x4308ec UBFM	X3, X12, #63, #62

(486) 0x4308f0 ADD	X13, X12, #8

(486) 0x4308f4 HINT	#0

(486) 0x4308f8 HINT	#0

(486) 0x4308fc HINT	#0

  (488) 0x430900 MADD	X16, X14, X4, XZR

  (488) 0x430904 ADD	X17, X21, X16

  (488) 0x430908 ADD	X0, X12, X16,LSL #3

  (488) 0x43090c UBFM	X18, X16, #60, #59

  (488) 0x430910 ADD	X5, X13, X17,LSL #3

  (488) 0x430914 ADD	X1, X18, #8

  (488) 0x430918 SUB	X30, X5, X0

  (488) 0x43091c SUB	X22, X30, #8

  (488) 0x430920 UBFM	X20, X22, #3, #63

  (488) 0x430924 ADD	X2, X20, #1

  (488) 0x430928 ANDS	X6, X2, #4224

  (488) 0x43092c B.EQ	4309d8

  (488) 0x430930 CMP	X6, #1

  (488) 0x430934 B.EQ	4309c0

  (488) 0x430938 CMP	X6, #2

  (488) 0x43093c B.EQ	4309b0

  (488) 0x430940 CMP	X6, #3

  (488) 0x430944 B.EQ	4309a0

  (488) 0x430948 CMP	X6, #4

  (488) 0x43094c B.EQ	430990

  (488) 0x430950 CMP	X6, #5

  (488) 0x430954 B.EQ	430980

  (488) 0x430958 CMP	X6, #6

  (488) 0x43095c B.EQ	430970

  (488) 0x430960 LDR	D0, [X0, #16]

  (488) 0x430964 SUB	X7, X1, X0

  (488) 0x430968 ADD	X0, X0, #8

  (488) 0x43096c STR	D0, [X7, X3]

  (488) 0x430970 LDR	D1, [X0, #16]

  (488) 0x430974 SUB	X8, X1, X0

  (488) 0x430978 ADD	X0, X0, #8

  (488) 0x43097c STR	D1, [X8, X3]

  (488) 0x430980 LDR	D2, [X0, #16]

  (488) 0x430984 SUB	X9, X1, X0

  (488) 0x430988 ADD	X0, X0, #8

  (488) 0x43098c STR	D2, [X9, X3]

  (488) 0x430990 LDR	D3, [X0, #16]

  (488) 0x430994 SUB	X10, X1, X0

  (488) 0x430998 ADD	X0, X0, #8

  (488) 0x43099c STR	D3, [X10, X3]

  (488) 0x4309a0 LDR	D4, [X0, #16]

  (488) 0x4309a4 SUB	X11, X1, X0

  (488) 0x4309a8 ADD	X0, X0, #8

  (488) 0x4309ac STR	D4, [X11, X3]

  (488) 0x4309b0 LDR	D5, [X0, #16]

  (488) 0x4309b4 SUB	X16, X1, X0

  (488) 0x4309b8 ADD	X0, X0, #8

  (488) 0x4309bc STR	D5, [X16, X3]

  (488) 0x4309c0 LDR	D6, [X0, #16]

  (488) 0x4309c4 SUB	X17, X1, X0

  (488) 0x4309c8 ADD	X0, X0, #8

  (488) 0x4309cc STR	D6, [X17, X3]

  (488) 0x4309d0 CMP	X5, X0

  (488) 0x4309d4 B.EQ	430a60

    (487) 0x4309d8 LDR	D7, [X0, #16]

    (487) 0x4309dc SUB	X6, X1, X0

    (487) 0x4309e0 ADD	X18, X0, #8

    (487) 0x4309e4 ADD	X11, X0, #16

    (487) 0x4309e8 SUB	X30, X1, X18

    (487) 0x4309ec ADD	X10, X0, #24

    (487) 0x4309f0 SUB	X22, X1, X11

    (487) 0x4309f4 ADD	X9, X0, #32

    (487) 0x4309f8 SUB	X20, X1, X10

    (487) 0x4309fc ADD	X8, X0, #40

    (487) 0x430a00 SUB	X18, X1, X9

    (487) 0x430a04 ADD	X7, X0, #48

    (487) 0x430a08 SUB	X17, X1, X8

    (487) 0x430a0c STR	D7, [X6, X3]

    (487) 0x430a10 SUB	X16, X1, X7

    (487) 0x430a14 ADD	X6, X0, #56

    (487) 0x430a18 LDR	D16, [X0, #24]

    (487) 0x430a1c SUB	X2, X1, X6

    (487) 0x430a20 ADD	X0, X0, #64

    (487) 0x430a24 STR	D16, [X30, X3]

    (487) 0x430a28 LDR	D17, [X11, #16]

    (487) 0x430a2c STR	D17, [X22, X3]

    (487) 0x430a30 LDR	D18, [X10, #16]

    (487) 0x430a34 STR	D18, [X20, X3]

    (487) 0x430a38 LDR	D19, [X9, #16]

    (487) 0x430a3c STR	D19, [X18, X3]

    (487) 0x430a40 LDR	D20, [X8, #16]

    (487) 0x430a44 STR	D20, [X17, X3]

    (487) 0x430a48 LDR	D21, [X7, #16]

    (487) 0x430a4c STR	D21, [X16, X3]

    (487) 0x430a50 LDR	D22, [X6, #16]

    (487) 0x430a54 STR	D22, [X2, X3]

    (487) 0x430a58 CMP	X5, X0

    (487) 0x430a5c B.NE	4309d8

  (488) 0x430a60 ADD	X4, X4, #1

  (488) 0x430a64 ADD	W5, W15, W4

  (488) 0x430a68 CMP	W19, W5

  (488) 0x430a6c B.GT	430900

(486) 0x430a70 LDP	X19, X20, [SP, #16]

(486) 0x430a74 LDP	X21, X22, [SP, #32]

(486) 0x430a78 LDP	X29, X30, [SP], #48

(486) 0x430a7c RET

(486) 0x430a80 ADD	W6, W6, #1

(486) 0x430a84 MOVZ	W7, #0

(486) 0x430a88 B	4308b4

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	update_halo.cpp:279-282
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:279-282

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.75 to 0.50 cycles (7.50x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 430860

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 430a80 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.22+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	update_halo.cpp:279-282
Module	exec

The function is defined in:

/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/context.h:69
/home/hbollore/qaas-runs/170-300-2310/intel/CloverLeafCXX/build/CloverLeafCXX/src/omp/update_halo.cpp:279-282

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.75 to 1.00 cycles (3.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.63
Overall L1	3.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.75 cycles. At this rate:

3% of peak load performance is reached (3.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 430860

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W0, W19, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W19, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 403530 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 4033c0 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W2, [X22, #12]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W3, W21, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W5, W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W6, W5, W20	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W7, W6, W20, W5	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 430a80 <_Z18update_halo_kerneliiiiRKSt5arrayIiLm4EES2_R10field_typePKii._omp_fn.22+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼update_halo_kernel(int, int, int, int, std::array const&, std::array const&, field_type&, int const*, int) [clone ._omp_fn.22]–	0.04	0.01
▼Loop 486 - update_halo.cpp:279-282 - exec–	0	0
▼Loop 488 - update_halo.cpp:281-282 - exec–	0.04	0.01
○Loop 487 - update_halo.cpp:281-282 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code